PLX Technology PEX 8311RDK, Hardware Reference Manual

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PEX 8311RDK Hardware Reference Manual, Version 0.90
36 © 2005 PLX Technology, Inc. All rights reserved.
(adds_4msb == 4'b0011) ? 4'b1011:
(adds_4msb == 4'b0100) ? 4'b0111: 4'b1111;
// byte enable encode for SRAM write cycles
wire [3:0] sram_bwn =({lwdrdn,a31_28}=='b1_0000)
? lben[3:0] : 4'b1111;
// store the upper address LA31 - LA28
always @ (posedge clk)
if (!adsn & (adds_4msb==4'b0000))
a31_28[3:0] <= adds_4msb[31:28];
// SRAM control state machine
parameter s0=2'b00, s1=2'b01, s2=2'b10, s3=2'b11;
always @ (posedge clk)
casex (state)
s0: begin
sramoen <=1;
oeb <='b1;
if (!adsn && !adds_4msb)
begin
sram_adds[9:2] <= adds_in[9:2];
sramcsn <= 0;
if (lwdrdn)
oer <= 'b0;
else
oer <= 'b1;
state <= s1;
end
else
begin
oer <= 'b1;
sramcsn <= 1;
state <= s0;
end
end
s1: if (lwdrdn && (!blastn))
begin
sram_adds[9:2] <=sram_adds[9:2]+1;
sramoen <=1;
sramcsn <=1;
oer <='b1;
oeb <='b1;
state <= s0;
end
else if (lwdrdn && blastn)
begin
if (sram_adds[9:2]== 'hfe)