PLX Technology PEX 8311RDK, Hardware Reference Manual

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PEX 8311RDK Hardware Reference Manual, Version 0.90
10 © 2005 PLX Technology, Inc. All rights reserved.
3.3.6 Hardware Memory Map
The PEX 8311RDK Local Bus memory map is shown in Table 3-3.
Table 3-3. PEX 8311RDK Processor/Local Bus Memory Map
Hex Address
Range
Device Chip Select Comments
FFFF FFFF
5000 0000
Unused _ Available
4FFF FFFF
4000 0000
Uncommitted FPGA
(FP2)
CS3#
Available &
Re-programmable
3FFF FFFF
3000 0000
Unused CS2#
Available &
Re-programmable
2FFF FFFF
2000 0000
Unused CS1#
Available &
Re-programmable
1FFF FFFF
1000 0000
J mode POM connector CS0#
32-bit, multiplexed
address/data bus
0FFF FFFF
0002 0000
Unused _ Available
0001 FFFF
0000 0000
Synchronous burst
SRAM
32Kx32
SRAMCS# 8-, 16-, or 32-bit access
3.4 PCI Express Interface
The PCI Express interface is a male card edge connector, based on the PCI Express Card
Electromechanical (CEM) Specification, Revision 1.0a for an x1 interface. In addition to the PCI Express
TX/RX pairs the card edge pr12 VDC and +3.3 VDC, RefClk, and PERST#. The PCI Express
TX/RX signals are laid out as 100-Ohm, controlled-impedance, microstrip-differential pairs. Trace length
mismatch within signal pairs is not greater than 0.005".
3.4.1 RefClk
PCI Express RefClk enters the PEX 8311RDK through the PCI Express card edge (male) connector.
RefClk is laid out as a 100-Ohm, controlled-impedance, microstrip-differential pair. Trace length mismatch
is not greater than 0.005".
Land is provided for the PCI Express RefClk to be generated onboard by an optional clock synthesizer
(U12), using a 25-MHz crystal for the seed frequency. The PEX 8311RDK can use the IC557G-03 part
from Integrated Circuit systems, Inc., though any comparable synthesizer is sufficient. RefClk is routed to
the PEX 8311. An unused 100MHz reference clock (REFCLK2) is also available from (U12). RefClk
routing is laid out as a 100-Ohm, controlled-impedance, microstrip-differential pair. Trace length mismatch
within this pair is less than 0.005".
When using the optional on board clock generator R12
and R13 should be removed to ensure that the
locally generated clock is not driven to the PCI Express edge connector (P1). In addition, R1 and R2
should be populated to route the on board clock to the PEX 8311.
The components for the on-board PCI Express clock circuitry are not assembled nor do they appear on
the BOM. Customers who require this feature must source and assemble the components themselves.
PLX takes no responsibility for boards damaged during this operation.
3.4.2 PERST#
PERST# is the fundamental Reset signal to the PEX 8311, from the PCI Express edge connector.