PLX Technology PEX 8311RDK, Hardware Reference Manual

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PEX 8311RDK Hardware Reference Manual, Version 0.90
© 2005 PLX Technology, Inc. All rights reserved.
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Table 4-9. Platform Flash to Xilinx interconnect
Connector
[pin]
JTAG
Signal
Plaftorm Flash
Signal [pin]
Link Resistor
(value)
FPGA signal
[pin]
Pull-up resistor
or jumper
Pull-down
resistor or
jumper
JP7 [2] Vref (2.5V) - - - - -
JP7 [4] F_TMS TMS [5] R164 (0) - - -
JP7 [6] F_TCK TCK [6] R165 (0) - - -
JP7 [8] F_TDO - R171 (0)
†
TDO [109] - -
JP7 [10] F_TDI TDI [4] R163 (0) - - -
JP7 [12,14] NC - - - - -
JP7 [1,3,5,7,9,
11,13]
GND - - - - -
- - D0 [1] R161 (0) DIN [63] - -
- - CLK [3] R162 (0) CCLK [71] - -
- - CF# [7] R166 (0) PROG_B [1]
JP5 NC + R180
(0) +R117 (4K7)
1
-
- - OE/RESET# [8] R167 (0) INIT_B [40]
JP4 NC + R292
(0) +R116 (4K7)
2
- - CE# [10] R169 (0) DONE [72]
R348 (0) + R358
(330 Ω )
3
- - GND [11] R168 (0) - -
- - TDO [17] R159 (56 Ω )
†,5
TDI [144] - -
- - VCCINT [18] R157 (0) - - -
- - VCCO [19] R154 (0)
4
- - -
- - VCCJ [20] R151(0)
4
- - -
JP7 [6] F_TCK TCK [6] R170 (56 Ω )
†
TCK [110]
JP7 [4] F_TMS TMS [5] R172 (56 Ω )
†
TMS[108]
R309 (0) M0 [62] - R379 (10K)
R297 (0) M1 [60] - R361 (10K)
R284 (0) M2 [57] - R375 (10K)
Notes:
1) If GPIO3 is to be used JP5 can be connected to position [1-2]. Care must be taken to avoid
accidentally placing the FPGA into programming mode or resetting the device.
2) If GPIO2 is to be used JP4 can be connected to position [1-2]. Care must be taken to avoid
accidentally placing the FPGA into programming mode or resetting the device.
3) R348 and R353 are only required if BitGen option DriveDONE = No – see the appropriate Xilinx
data sheet for more details. Ideally pin 3 or pin 6 of RN10 should be lifted if R348 and R353 are
used.
4) R154 and R151 are used when 3.3V programming is required. Other programming voltages are
possible but will require pull’s on the Xilinx array to be modified appropriately. See the Xilinx data
sheets for further details.
5) If the Xilinx FPGA is not linked to the scan chain then remove R159 and add R158 (0). This will
link the TDO of the Platform Flash to the JTAG connector TDO pin (F_TDO).
As noted above, in Table 4-9 the JTAG TDO output from the platform flash is routed to the TDI input of
the Xilinx FPGA i.e. the Program Flash is the first device in the chain. The scan chain can also be
configured so that Xilinx device is the first device in the chain by removing R159, R163 and R171 and
populating R158 (0), R160 (0) and R173 (
56 Ω
).
4.4.2.4 Uncommitted FPGA power supplies
The device mounted onto FP2 may require a voltage level not provided by the voltage regulators
assembled on the RDK. To accommodate this, the uncommitted USRVCC circuit can be populated with
an appropriate voltage regulator.
Although the schematics show U14 to be a 2.5V regulator any comparable regulator which can fit the
SOT-223 layout can be used.