PLX Technology PEX 8311RDK, Hardware Reference Manual

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PEX 8311RDK Hardware Reference Manual, Version 0.90
16 © 2005 PLX Technology, Inc. All rights reserved.
4.1 Monitoring Points, Test headers, Indicators, Control, and DIP Switch Summary
This section summarizes the interfaces available on the PEX 8311RDK for controlling and monitoring
PEX 8311 performance.
4.1.1 Monitoring Points
ƒ Six ground test points (TP3-8), are scattered across the PEX 8311RDK to provide probe
reference points
ƒ Voltages to the PEX 8311 can be monitored at the following locations:
ƒ J8 (1.5 VCC)
ƒ J9 (2.5 VCC)
ƒ J7 (3.3 VCC)
ƒ Three 3.3 VCC test points (TP9-11), are scattered across the PEX 8311RDK to allow voltage
monitoring.
ƒ TP1 is connected to the PEX 8311 PWR_OK output
ƒ
TP2 can be used to monitor the PEX8311 internal clock
ƒ External power can be monitored at the ATX connector (J4)
ƒ J1 provides access to the PEX 8311 JTAG port; TCK, TDI, TDO, and TMS
ƒ LAH 1-6 Logic analyzer test headers to connect to monitor local bus activity, see Section 4.1.2.1
Test Headers
4.1.2 Headers
4.1.2.1 Test Headers
The RDK board has six (6) 0.1”, 2x10 logic analyzer headers (LAH1-6) that follow the HP format and can
be used for probing or prototype area extension. All PEX 8311 Local Bus signals, configuration and status
signals are well arranged within these headers. Headers LAH2 and LAH3 contain Local Bus address
signals. Headers LAH4 to LAH6 contain Local Bus data signals. Headers LAH1 and LAH5 contain Local
Bus control and status signals. These headers do not provide any power source. Schematic page 5
provides the connector signal details.
4.1.2.2 JTAG Headers
There are two independent JTAG test ports on the PEX 8311 RDK. J1 is a 0.1”, 6 x 1 header which
allows access to the PEX 8311 JTAG interface. This can be used to check connectivity of the device and
to allow customers to develop their own test programs. With the exception of BSDL models PLX does not
provide any additional boundary scan test software for the PEX 8311 or the PEX 8311 RDK.
J2 is a 0.1” 9 x 1 header which is connected directly to the Xilinx CPLD (U10). This header allows the
CPLD to be re-programmed by the user at any time. PLX does not provide the programming software or
the lead to allow re-programming of the CPLD.
By reprogramming the CPLD the user can change the functionality of the board. However, customers
who re-program the CPLD do so at their own risk. PLX takes no responsibility for boards damaged or
rendered inoperable while re-programming the CPLD.