PLX Technology PEX 8311RDK, Hardware Reference Manual

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PEX 8311RDK Hardware Reference Manual, Version 0.90
vi © 2005 PLX Technology, Inc. All rights reserved.
7.1 Verilog Code .................................................................................................................................. 35
8. References........................................................................................................................................... 39
9. Bill of Materials / Schematics ............................................................................................................... 41
F
IGURES
Figure 1-1. PEX 8311RDK – Component Side View.................................................................................... 1
Figure 3-1. PEX 8311RDK Hardware Architecture ...................................................................................... 4
Figure 4-1. PEX 8311RDK Component Placement.................................................................................... 15
Figure 4-2. PEX 8311RDK Decoupling Capacitor Footprints..................................................................... 18
Figure 4-3. PEX 8311RDK Stackup ........................................................................................................... 18
T
ABLES
Table 3-1. Long Serial EEPROM Load Registers ........................................................................................ 6
Table 3-2. Extra Long Serial EEPROM Load Registers............................................................................... 7
Table 3-3. PEX 8311RDK Processor/Local Bus Memory Map .................................................................. 10
Table 3-4. PEX 8311RDK LED Indicators.................................................................................................. 11
Table 3-5. PEX 8311RDK Power supply currents...................................................................................... 12
Table 3-6. PEX 8311RDK Power jumper and resistor options................................................................... 12
Table 4-1. PEX 8311RDK Default Jumper Settings ................................................................................... 17
Table 4-2. Layer thickness ......................................................................................................................... 19
Table 4-3. Six (6) Surface Mount Footprints .............................................................................................. 19
Table 4-4. Uncommitted FPGA resistor configuration................................................................................ 21
Table 4-5. Altera Uncommitted FPGA JTAG interconnections .................................................................. 25
Table 4-6. Xilinx Uncommitted FPGA JTAG interconnections ................................................................... 26
Table 4-7. Programming the Altera Uncommitted FPGA through the GPIO.............................................. 27
Table 4-8. Programming the Xilinx Uncommitted FPGA through the GPIO............................................... 28
Table 4-9. Platform Flash to Xilinx interconnect......................................................................................... 29
Table 5-1. RDK Board Mode Configuration................................................................................................ 31
Table 9-1. PEX 8311RDK Bill Of Materials ................................................................................................ 41