A
A
B
B
C
C
D
D
E
E
4
4
3
3
2
2
1
1
5VCC
RESET CKT
PCI9054
Universal PCI Edge Card Connector (3.3V/5V)
GND
Suggested Board Layout
DB9
LEDs
BGA
0.05" pitch
26X26
FLASH
32PLCC
CPLD
SYNC.
SRAM
1
1
1
Clock
OSC
SERIAL
EPROM
DC/DC
RS232 Interface
1
1
1
1
Clock Buffer
BGA
1.5mm pitch
20X20
208/144/80-pin QFP
FP21-FP23
0.5mm pitch
84, 68, 44, 28 pin
PLCCs
U7
U11
S1
16-pin
SOIC
16-pin
SOIC
FP9
FP10
FP5
FP8
44-pin
TQFP
44-pin
TQFP
FP11
FP12
28-pin
SOIC
BGA
1.0mm pitch
25X25
FP13
FP14
48-pin
SSO
P
48-pin
SSO
P
240/176/100-pin QFP
FP15-FP17
0.5mm pitch
160/112-pin QFP
FP26-FP28
0.65mm pitch
30X25 0.1" c-c
Through hole
Ptrototype
Area
FP29
FP30
54-pin
TSOP
54-pin
TSOP
JP1
208/144/80-pin QFP
FP18-FP20, 0.5mm pitch
on the back.
176/100-pin QFP,
FP24-FP25,
0.5mm pitch on
the back.
128-pin 0.4mm pitch
TQFP on the back.
RJ45 & USB
connectors
Note:
1. Control Signal Connector (LAH5)
2. Control Signal Connector (LAH6)
3. Data Bus Connector (LAH3)
4. Data Bus Connector (LAH4)
5. Address Bus Connector (LAH1)
6. Address Bus Connector (LAH2)
7. Marked as is ptototyping area
U2
U10
U9
U1
LAH6
LAH5
LAH1
LAH2
LAH3
LAH4
U3-4
U5
U6
12.283"
5.20" max.
J3 JPOM
Connector
0.295"
0.190"
3.362" between center
of two Tab holes
28-pin
SOIC
FP11
FP11
BGA1
3.3V
GND
3.3V
PCI9054RDK-LITE
003
PLX TECHNOLOGY, INC.
870 Maude Ave, Sunnyvale, CA 94085
Custom
13
13
Thursday, October 21, 2004
www.plxtech.com
Title
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Document Number
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Date:
Sheet
of
Summary of Contents for PCI 9054RDK-LITE
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