PLX Technology PCI 9054RDK-LITE, Hardware Reference Manual

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PCI 9054RDK-LITE Hardware Reference Manual v1.3
© 2006 PLX Technology, Inc. All rights reserved.
7
Table 3-2 Long Serial EEPROM Load Registers
Serial
EEPROM
Offset
Serial
EEPROM
Value (hex)
Description Register Bits Affected
0h 5406 Device ID PCIIDR[31:16]
2h 10B5 Vendor ID PCIIDR[15:0]
4h 0680 Class Code PCICCR[23:8]
6h 000B Class Code, Revision PCICCR[7:0] / PCIREV[7:0]
8h 0000 Maximum Latency, Minimum Grant PCIMLR[7:0] / PCIMGR[7:0]
Ah 0100 Interrupt Pin, Interrupt Line Routing PCIIPR[7:0] / PCIILR[7:0]
Ch 0000 MSW of Mailbox 0 (User Defined) MBOX0[31:16]
Eh 0000 LSW of Mailbox 0 (User Defined) MBOX0[15:0]
10h 0000 MSW of Mailbox 1 (User Defined) MBOX1[31:16]
12h 0000 LSW of Mailbox 1 (User Defined) MBOX1[15:0]
14h FFFE MSW of Range for PCI-to-Local Address Space 0 LAS0RR[31:16]
16h 0000 LSW of Range for PCI-to-Local Address Space 0 LAS0RR[15:0]
18h 2000
MSW of Local Base Address (Re-map) for
PCI-to-Local Address Space 0
LAS0BA[31:16]
1Ah 0001
LSW of Local Base Address (Re-map) for
PCI-to-Local Address Space 0
LAS0BA[15:0]
1Ch 0120 MSW of Mode/DMA Arbitration Register MARBR[31:16]
1Eh 0000 LSW of Mode/DMA Arbitration Register MARBR[15:0]
20h 0030 MSW of Local Bus Big/Little Endian Descriptor PROT_AREA [15:0]
22h 0500 LSW of Local Bus Big/Little Endian Descriptor LMISC [7:0] / BIGEND [7:0]
24h 0000 MSW of Range for PCI-to-Local Expansion ROM EROMRR[31:16]
26h 0000 LSW of Range for PCI-to-Local Expansion ROM EROMRR[15:0]
28h 0000
MSW of Local Base Address (Re-map) for
PCI-to-Local Expansion ROM
EROMBA[31:16]
2Ah 0000
LSW of Local Base Address (Re-map) for
PCI-to-Local Expansion ROM
EROMBA[15:0]
2Ch 4343
MSW of Bus Region Descriptors for
PCI-to-Local Space 0 and Expansion ROM
LBRD0[31:16]
2Eh 00C3
LSW of Bus Region Descriptors for
PCI-to-Local Space 0 and Expansion ROM
LBRD0[15:0]
30h 0000 MSW of Range for Direct Master-to-PCI DMRR[31:16]
32h 0000 LSW of Range for Direct Master-to-PCI DMRR[15:0]
34h 4000
MSW of Local Base Address for
Direct Master-to-PCI Memory
DMLBAM[31:16]
36h 0000
LSW of Local Base Address for
Direct Master-to-PCI Memory
DMLBAM[15:0]
38h 5000
MSW of Local Bus Address for
Direct Master-to-PCI I/O Configuration
DMLBAI[31:16]
3Ah 0000
LSW of Local Bus Address for
Direct Master-to-PCI I/O Configuration
DMLBAI[15:0]
3Ch 0000
MSW of PCI Base Address (Re-map) for
Direct Master-to-PCI Memory
DMPBAM[31:16]
3Eh 0000
LSW of Local Bus Address for
Direct Master-to-PCI Memory
DMPBAM[15:0]
40h 0000
MSW of PCI Configuration Address Register for
Direct Master-to-PCI I/O Configuration
DMCRGA[31:16]
42h 0000
LSW of PCI Configuration Address Register for
Direct Master-to-PCI I/O Configuration
DMCFGA[15:0]