PLX Technology PCI 9054RDK-LITE, Hardware Reference Manual

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5. CPLD VERILOG CODE
//==============================================================
// 8/12/99
//
// Synchronous SRAM controller for PLX PCI 9054 mode C and J.
// 128K byte (32K x 32 bit) synchronous SRAM is used.
// The memory map for the sync. SRAM is 2000_0000 - 2001_FFFFh.
// A partial memory decode is used. The decode only involves
// address lines A31 to A28 (or A31-A29 and LD28 in J mode)
//
// 2/13/02
//
// Changed the "ready" signal to tri-state when there is no
// access to the SRAM.
//
//==============================================================
module SRAMCTR
(
// local bus signals
CLK_50MHZ, // clock to PCI9054, SRAM and controller
ADS_, // address strobe from 9054
BLAST_, // burst last from 9054
LBE_, // byte enable from 9054
LWDRD_, // local bus read/write
ADDR_IN, // local bus address inputs
ADDR_4MSBS, // local bus address A31 - A28
READY_, // ready signal to PLX PCI9054
// address and control signals to synchronous SRAM
SRAM_ADDR, // address outputs to the sync. SRAM
SRAMCS_, // chip select to the SRAM
SRAMOE_, // output enable to the SRAM
SRAM_BW_, // byte enables in SRAM write cycle
//bus
arbitration
LHOLD, // bus hold request from PLX PCI9054
LHOLDA, // bus hold acknowledge
LBR, // two local bus request
LBG, // two local bus grant
// chip selects
CS_ // four chip select outputs
);
PCI 9054RDK-LITE Hardware Reference Manual v1.3
© 2006 PLX Technology, Inc. All rights reserved.
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