PLX Technology PCI 9054RDK-LITE, Hardware Reference Manual

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PCI 9054RDK-LITE Hardware Reference Manual v1.3
© 2006 PLX Technology, Inc. All rights reserved.
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// store the upper address LA31 - LA28
always @ (posedge CLK_50MHZ)
if (LHOLD & !ADS_ & (ADDR_4MSBS==4'b0010))
A31_28[3:0] = ADDR_4MSBS[31:28];
else
A31_28[3:0]
= A31_28;
// local bus arbitration
always @(posedge CLK_50MHZ)
if (LHOLD)
LHOLDA = LHOLD;
else
LHOLDA
= 0;
always @ (posedge CLK_50MHZ)
if (!LHOLD & LBR[1])
LBG[1] = LBR[1];
else
LBG[1]
= 0;
always @ (posedge CLK_50MHZ)
if (!LBR[1] & LBR[0])
LBG[0] = LBR[0];
else
LBG[0]
= 0;
// State definition
parameter s0 = 4'b0000; // idle
parameter s1 = 4'b0001; // cycle start
parameter s2 = 4'b0010; // single cycle wait state
parameter s3 = 4'b0011; // single cycle last state
parameter s4 = 4'b0100; // burst cycle wait state
parameter s5 = 4'b0101; // burst cycle repeat state
parameter s6 = 4'b0110; // burst cycle last state
// SRAM address counter
always @ (posedge CLK_50MHZ)
if (!ADS_)
SRAM_ADDR[16:2] = ADDR_IN[16:2];
else if (BLAST_ && !((currentstate == s1) && LWDRD_))
SRAM_ADDR[12:2] = SRAM_ADDR[12:2] +1;
else
SRAM_ADDR[16:2]
= SRAM_ADDR[16:2];