PLX Technology PCI 9054RDK-LITE, Hardware Reference Manual

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2. SYSTEM ARCHITECTURE
As shown in Figure 2-1, the RDK board contains The RDK is shipped with C mode as the default.
Once the board is correctly installed into a PC
computer system, the PCI master, such as the
Intel microprocessor in the PC motherboard, can
perform single memory read/write cycles,
multiple memory read/write cycles, and
continuous burst memory read/write cycles
from/to the on-board synchronous SRAM in
direct slave mode.
•
PCI 9054 PCI I/O Accelerator
•
Four components (CPLD, SRAM, Test
Headers, and JPOM connector) connected
to the PCI 9054 Processor/Local Bus
•
Four commonly used hardware modules
(LEDs, Flash ROM Socket, Reset Circuitry,
and RS232 Interface)
Four hardware modules on the RDK provide
some basic hardware building blocks for almost
any PCI 9054 design.
•
More than 75% of the board area provides
many carefully-selected prototyping
footprints.
The thirty (30) surface mount footprints, and
three (3) BGA landscapes support industry-
leading 16-bit and 32-bit embedded processors
and DSPs from Hitachi, Motorola, IDT, TI, IBM
and Analog Devices. Also, the PLCC footprints
and PQFP footprints cover various common
packages of CPLDs and FPGAs and PLX chips
such as the PCI 9054.
RS232
Interface
Flash ROM
Socket
Debug & Status
LEDs
Reset Circuitry
PCI 9054
CPLD
Test
Headers
J Mode
POM
Connector
Synchronous
SRAM 32K
x32
30 Surface Mount
Footprints
3 Common Pitch BGA
Landscapes
30x25 0.1" Through Hole
Prototyping Area
RJ45 and type A USB
Connector
PCI Bus, 32 Bit, 33 MHz
Loc
al B
u
s
32
-bit
,
50
MHz
Figure 2-1. PCI 9054RDK-LITE System Architecture
PCI 9054RDK-LITE Hardware Reference Manual v1.3
© 2006 PLX Technology, Inc. All rights reserved.
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