PCI 9054RDK-LITE Hardware Reference Manual v1.3
© 2006 PLX Technology, Inc. All rights reserved.
21
always @ (currentstate)
casex(currentstate)
s0:
begin
oer
=1;
SRAMCS_=1;
SRAMOE_=1;
end
s1:
begin
oer
=1;
SRAMCS_=0;
SRAMOE_=1;
end
s2:
begin
oer=0;
SRAMCS_=0;
if
(LWDRD_==0)
SRAMOE_=0;
else
SRAMOE_=1;
end
s3:
begin
oer=1;
SRAMCS_=1;
SRAMOE_=1;
end
s4:
begin
oer=0;
SRAMCS_=0;
if
(LWDRD_==0)
SRAMOE_=0;
else
SRAMOE_=1;
end
s5:
begin
oer=0;
SRAMCS_=0;
if
(LWDRD_==0)
SRAMOE_=0;
else
SRAMOE_=1;
end
s6:
begin
oer=1;
SRAMCS_=1;
SRAMOE_=1;
end
endcase
always @(posedge CLK_50MHZ)
currentstate
<=
nextstate;
endmodule
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