PLX Technology PCI 9054RDK-LITE, Hardware Reference Manual

Page: 17 / 47

PCI 9054RDK-LITE Hardware Reference Manual v1.3
© 2006 PLX Technology, Inc. All rights reserved.
9
3.4 Synchronous SRAM
A 100-pin 7.5ns 32K x 32 Micron SyncBurst
SRAM is used as data storage in the RDK. It is
used for demonstration of continuous burst
cycles from the PCI 9054 chip. It takes 15
address lines (SA16-SA2) from the SRAM
controller implemented in the Altera CPLD. The
data lines of the SRAM are directly connected to
the PCI 9054 local data bus (LD31-LD0). During
memory burst cycles, the SRAM performs
continuous single read cycles or single write
cycles. The SRAM controller does all the timing
conversion and generates the address to the
SRAM.
3.5 Altera CPLD
The CPLD used in this RDK is a 4ns Altera
EPM7064AE device. Referring to Figure 3-1,
PCI 9054RDK-LITE hardware diagram, there
are three functional blocks inside the CPLD:
SRAM controller, external arbiter and chip select
generator. During memory cycles, the SRAM
controller generates all control signals, SRAM
chip select (SRAMCS#), SRAM output enable
(SRAMOE#), and SRAM byte write enables
(SRAM_BW_[3:0]) to the Synchronous SRAM.
During burst memory cycles, the SRAM
controller will latch the 15 starting address bits
(when ADS# is low) and use its built-in 11-bit
internal address counter to advance the
addresses to the synchronous SRAM. This
effectively divides the SRAM into 16 “pages” of
memory. It is important to note that the
BTERM# signal is not implemented in the SRAM
controller, thus, software should take care not to
have this counter overflow from 0x7FF to 0x000,
lest the beginning locations of a given “page” be
overwritten, on write cycles. A more appropriate
method would involve generating a BTERM#
signal each time all 11 bits of the counter are
1’s, thus forcing the PCI 9054 to break up the
burst and generate a new address cycle.
On the PCI 9054 side, the SRAM controller
generates the active low ready signal (READY#)
to terminate PCI 9054 memory cycles.
The external arbiter in the CPLD accepts two
Processor/Local Bus request signals, LBR[1:0],
and the bus request from the PCI 9054 LHOLD
signal, and it generates bus grant signals,
LBG[1:0], to the Processor/Local Bus masters,
and LHOLDA to PCI 9054 chip.
Also, the built-in chip select generator in the
CPLD provides four active-low chip select
signals to the devices on the Processor/Local
Bus in addition to the chip select (SRAMCS#) to
the synchronous SRAM. The chip select signals
are partially decoded from the upper most four
address lines (LA31-LA28) on the
Processor/Local Bus. They can be re-
programmed by altering the Verilog code in the
CPLD.
An important system consideration is that
some systems may experience booting
difficulty because BIOS attempts to access
non-existent Expansion ROM at offset 0000
0000H, if no eeprom is present or the eeprom
is blank. In this case, the local bus will hang
because READY# is not generated for that
address range. This can be solved in a
number of ways (see Design Notes for this
RDK on the HDK disk or on the PLX Website,
for a hardware-only solution). A
programmable solution is to modify the
CPLD code to either remap or mirror the
SRAM from 2000 0000H to 0000 0000H.
3.6 Test Headers
Six HP logic analyzer headers are implemented
with standard 0.1”, 2x10 pin-out. In this RDK,
they serve two different functions. One is for
easy probing. All PCI 9054 Processor/Local Bus
signals, configuration and status signals are well
arranged with these headers. Headers LAH1
and LAH2 contain Processor/Local Bus address
signals. Headers LAH3 and LAH4 contain
Processor/Local Bus data signals (or
multiplexed address/data signals in J mode).
Headers LAH5 and LAH6 carry Processor/Local
Bus contain control and status signals. Second,
these headers are centered on 0.1” grid
spacing.
Designers can use these headers to connect to
a standard prototyping board for additional
prototyping. The headers do not provide any
power source; therefore this must be connected
separately for prototyping daughter boards.