PLX Technology PCI 9054RDK-LITE, Hardware Reference Manual

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PCI 9054RDK- LITE Hardware Reference Manual v1.3
18 © 2006 PLX Technology, Inc. All rights reserved.
// port declarations
output [16:2] SRAM_ADDR;
output READY_;
output SRAMCS_;
output SRAMOE_;
output [3:0] SRAM_BW_;
output LHOLDA;
output [1:0] LBG;
output [3:0] CS_;
input CLK_50MHZ;
input ADS_, BLAST_;
input [3:0] LBE_;
input LWDRD_;
input [16:2] ADDR_IN;
input [31:28] ADDR_4MSBS;
input LHOLD;
input [1:0] LBR;
reg [16:2] SRAM_ADDR;
reg [1:0] LBG;
reg LHOLDA;
reg SRAMCS_;
reg SRAMOE_;
// internal variables
reg [3:0] A31_28;
reg [2:0] currentstate, nextstate;
reg oer;
bufif0
(READY_,oer,oer);
// chip selects
// Four most upper address lines, A31-A28, are used to
// generate four chip select signals for the board. They
// are CS[3:0] with address as
//
// CS_0: 4000_0000h
// CS_1: 5000_0000h
// CS_2: 6000_0000h
// CS_3: 7000_0000h
wire [3:0] CS_ = (ADDR_4MSBS == 4'b0100) ? 4'b1110:
(ADDR_4MSBS == 4'b0101) ? 4'b1101:
(ADDR_4MSBS == 4'b0110) ? 4'b1011:
(ADDR_4MSBS == 4'b0111) ? 4'b0111: 4'b1111;
// byte enable encode for SRAM write cycles
wire [3:0] SRAM_BW_ =({LWDRD_,A31_28}=='b1_0010)
? LBE_[3:0] : 4'b1111;