PRA-BD11
93
5
6
7
8
5
6
7
8
C
D
F
A
B
E
No.
Pin Name
I/O
Pin Function
53
Vcco
−
I/O power supply (3.3V)
54
M2
I
Configuration setting (default "L", master serial mode)
55
N.C.
−
N.C.
56
N.C.
−
N.C.
57
N.C.
−
Reserve
58
EAPKT8
−
Arbitrary (addition) data input of GS9023
59
EAPKT7
−
Arbitrary (addition) data input of GS9023
60
EAPKT6
−
Arbitrary (addition) data input of GS9023
61
EAPKT5
−
Arbitrary (addition) data input of GS9023
62
EAPKT4
−
Arbitrary (addition) data input of GS9023
63
EAPKT3
−
Arbitrary (addition) data input of GS9023
64
GND
−
Digital GND
65
Vcco
−
I/O power supply (3.3V)
66
Vccint
−
Core power supply (2.5V)
67
EAPKT2
−
Arbitrary (addition) data input of GS9023
68
EAPKT1
−
Arbitrary (addition) data input of GS9023
69
EAPKT0
−
Arbitrary (addition) data input of GS9023
70
EAPKTE
O
Arbitrary (addition) data enable input of GS9023 L: Disable (default), H: Enable
71
EARST
O
Reset input of GS9023 (Active Low) L: Reset , H: Normal operation
72
GND
−
Digital GND
73
EAVM0
O
Video format setting of GS9023
74
EAVM1
O
Video format setting of GS9023
75
EAVM2
O
Video format setting of GS9023
76
Vccint
−
Core power supply (2.5V)
77
CLK18R
I
18.432MHz clock input for RS-232C
78
Vcco
−
I/O power supply (3.3V)
79
GND
−
Digital GND
80
CLK27F
I
27MHz clock input for AVIB communication
81
EAAM0
O
Audio format setting of GS9023 (default, EAAM [2:0] = 000, 24bit, left-justified)
82
EAAM1
O
Audio format setting of GS9023 (default, EAAM [2:0] = 000, 24bit, left-justified)
83
EAAM2
O
Audio format setting of GS9023 (default, EAAM [2:0] = 000, 24bit, left-justified)
84
EAMUTE
O
Audio mute of GS9023 L: Normal operation (default), H: Mute
85
GND
−
Digital GND
86
EAEDH
O
EDH insert setting of GS9023 L: Invalid (default), H: Valid
87
EATRS
O
Timing reference code setting of GS9023 L: Invalid (default), H: Valid
88
EAA0
O
Host I/F address of GS9023
89
EAA1
O
Host I/F address of GS9023
90
EAA2
O
Host I/F address of GS9023
Host I/F address of GS9023
91
Vccint
−
Core power supply (2.5V)
92
Vcco
−
I/O power supply (3.3V)
93
GND
−
Digital GND
94
EAA3
O
95
EACS
O
Host I/F chip select of GS9023 (Active Low)
96
EAWE
O
Host I/F write enable of GS9023 (Active Low)
97
EARE
O
Host I/F read enable of GS9023 (Active Low)
98
EAD7
I/O
Host I/F data input/output of GS9023
99
EAD6
I/O
Host I/F data input/output of GS9023
100 EAD5
I/O
Host I/F data input/output of GS9023
101 EAD4
I/O
Host I/F data input/output of GS9023
102 EAD3
I/O
Host I/F data input/output of GS9023
103 GND
−
Digital GND
104 CFDONE
O
DONE signal for configuration L: During configuration, H: Configuration completion
Summary of Contents for PRA-BD11
Page 19: ...PRA BD11 19 5 6 7 8 5 6 7 8 C D F A B E A 3 4 ...
Page 21: ...PRA BD11 21 5 6 7 8 5 6 7 8 C D F A B E ...
Page 23: ...PRA BD11 23 5 6 7 8 5 6 7 8 C D F A B E B 1 2 2 2 B 2 2 B 2 2 B 2 2 B 2 2 B 2 2 B 2 2 B 2 2 B ...
Page 25: ...PRA BD11 25 5 6 7 8 5 6 7 8 C D F A B E B 2 2 1 2 B 1 2 B 1 2 B 1 2 B ...
