PRA-BD11
76
1
2
3
4
1
2
3
4
C
D
F
A
B
E
27
A/D
I
Parallel port add ress/data bus control. When HIGH, the parallel port is used for address input.
When LOW, the parallel port is used for data input or output. In I
≤
C mode, this pin must be set
LOW.
28
CS
I
Parallel port chip select. When CS is LOW and R/W is HIGH, the GS9020A drives the address/
data bus. When CS is LOW and R/W is LOW, the user should drive the address/data bus.
When CS is HIGH, the address/data bus is in a high impedance st ate (Hi - Z). In I
≤
C mode, this
pin must be set HIGH.
31
RESET
I
Reset. When LOW, the internal control circuitry is reset.
32 - 35
STD[3:0]
O
Video standards indication as descri bed i n section 1.4
36 - 40
FL[4:0]
I/O
EDH flag dat a port to allow acces s to the EDH flags.
41, 42
S[1:0]
I/O
Control bits which select whether FF, AP, or ANC EDH flags are active on the EDH flag dat a
port (FL[4:0]). In FLAG_MAP mode, the S[1:0] pins becom e outputs (see device desc ription).
43
F_R/W
I
Flag p ort read/write control. When HIGH, FL[4:0] are configured as outputs allowing EDH flags
to be read from the device. When LOW, FL[4:0] are configured as inputs allowing EDH flags to
be overwritten in the outgoing EDH packet. In FLAG_MAP mode this pin must be set HIGH.
44
INTERRUPT
O
Interrupt output. This output goes low when EDH errors occur. This pin is an open drain output
and requires an external pullup resistor. If this output is not used, a pullup resistor is not
required.
45
FLYWDIS
I
Flywheel disable. When HIGH, the internal flywheel is disabled. When LOW, the internal
flywheel is enabled.
46
NO_EDH
O
No EDH present indication. When HIGH, indicates EDH packet s are not present in the
incoming d ata stream.
47
FIFO_RESET
O
FIFO Reset output. Asserted LOW during the TRSID word for composite standards and the
EAV or SAV word for component standards.
48
PCLKOUT
O
Parallel clock output.
52-60,49
DOUT[9:0]
O
Parallel digital video dat a outputs.
61
V
O
Vertical sync indication.
62
H
O
Horizontal sync indication.
63 - 65
F[2:0]
O
Field indication. F2 is the MSB.
66
FLAG_MAP
I
FLAG_MAP mode enable. When HIGH, FLAG_MAP mode is enabled.
When LOW, FLAG_MAP mode is disabled.
70, 71
SDO/SDO
O
Differential serial data outputs.
73
VBLANKS/L
I
Vertical blanking interval control. For NTSC signals, when VBLANKS/L is set LOW the 19 line
blanking interval is selected and when set HIGH the 9 line blanking interval is selected. For
PAL D2 signals, when VBLANKS/L is set LOW the 17 line blanking interval is selected and
when set HIGH the 7 line blanking interval is selected. For PAL component signals VBLANKS/L
should b e set LOW.
74
BYPASS_EDH
I
Bypass EDH control. When HIGH, the device allows the EDH packet to pass through
unaltered.
75
SDOMODE
I
Serial data output control. When LOW, the serial data output is re-serialized processed dat a.
When HIGH, the serial data output is the looped through serial input. After changi ng
SDOMODE, the GS9020A must be reset for proper operat ion.
76
BLANK_EN
I
Blanking enable. When LOW, incoming data words are set to appropriate blanking levels.
77
ANC_CHKSM
I
Ancillary checksum updat ing enabl e. When HIGH, ancillary checksum updat ing is enabled.
NUMBER
SYMBOL
TYPE
DESCRIPTION
Pin Descriptions
Summary of Contents for PRA-BD11
Page 19: ...PRA BD11 19 5 6 7 8 5 6 7 8 C D F A B E A 3 4 ...
Page 21: ...PRA BD11 21 5 6 7 8 5 6 7 8 C D F A B E ...
Page 23: ...PRA BD11 23 5 6 7 8 5 6 7 8 C D F A B E B 1 2 2 2 B 2 2 B 2 2 B 2 2 B 2 2 B 2 2 B 2 2 B 2 2 B ...
Page 25: ...PRA BD11 25 5 6 7 8 5 6 7 8 C D F A B E B 2 2 1 2 B 1 2 B 1 2 B 1 2 B ...
