Pioneer PRA-BD11, Service Manual

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PRA-BD11
73
5 6 7 8
5 6
7
8
C
D
F
A
B
E
NUMBER SYMBOL TYPE DESCRIPTION
1-10 PD9 - PD0 I CMOS or TTL compatible parallel data inputs. PD0 is the LSB and PD9 is the MSB.
11 PCLKIN I CMOS or TTL compatible parallel clock input.
12 V
EE3
- Most negative power supply connect ion for parallel data and clock inputs.
13 V
CC3
- Most positive power supply connect ion for parallel data and clock inputs.
14 RSV2 I Reserved pin. Do not connect .
15, 19, 21, 27,
28, 30, 32, 37
NC I No connect.
16 RSV1 I Reserved pin. Always connect to V
CC
.
17 V
CC2
- Most positive power supply connect ion for internal logic and digital circuits.
18 V
EE2
- Most negative power supply connect ion for internal logic and digital circuits.
20 LOCK O TTL level which is high when the internal PLL is locked.
22 R
SET
I External resistor used to set the data output amplitude for SDO and SDO.
23, 26, 29 V
EE
- Most negative power supply connect ion for shielding (not connect ed).
24, 25 SDO, SDO O Primary, current mode, 75 cabl e driving output (inverse and true)
31 BYPASS I When high, the SMPTE Scrambler and NRZ encoder a re bypasse d.
Pin Descriptions
Ω
33 RESET I Resets the scrambler when asserted.
34 V
CC1
- Most positive power supply connect ion for analog circuits.
35 V
EE1
- Most negative power supply connect ion for analog circuits.
36, 38 R
VCO
+, R
VCO
- I Differential VCO current setting resistor that sets the VCO frequency.
39, 43 V
EE
- Most negative power supply connect ion (substrate).
40 LBWC I TTL level loop band width control that adjusts the PLL bandwidth to optimize for lowest
jitter. If the pin is set to ground the loop bandwidth i s BW
MIN
. If the pin is left floating, the
loop band width is approximately 3 BW
MIN
, if the pin is tied to V
CC
the loop bandwidths
app roximately10 BW
MIN
41, 42 LF+, LF- I Differential loop filter pins to optimize loop transfer performance at low loop bandwidths
(NC if not used).
44 SYNC DIS I Sync detect disable. Logic high di sables sync detection. Logic low allows 8 bit operation
by mapp ing 000-003 to 000 and 3FC-3FF to 3FF.