Phytec phyCORE-PXA270, Hardware Manual

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Carrier Board phyCORE-PXA270
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PHYTEC Meßtechnik GmbH 2006 L-668e_1
IDE control register 1 is used to set the memory interface and the
DMA access. Since a hard drive only supports the TruIDE mode of a
CF card interface, this has a fixed setting in register bit 0. The
PXA270 controller's PCMCIA interface does not support TrueIDE
mode. Therefore the /IDE_PCE1 signal is activated with A11='0' and
the /IDE_PCE2 signal is activated with A11='1'. Both signals are
active during 8-bit as well as 16-bit accesses. As an option the IDE
interface can also run in DMA mode. The DMA mode is activated by
setting bit DMAENA. The free DMA channel can be selected in
register DMA0/1. The DACK signal is generated if A21=1 and
A13=0.
REG ADDR D7 D3 D2 D1 D0
IDE 1 0x20001002 Res DMA0 DMAEN RES IDE/MEM
RW R/W=0 R=0/W=0 R/W R/W=0 R=1/W=1
Signal
Name XDREQ_0 xIDE_DRE
Q
internal
Table 21: IDE Control Register 1
IDE/MEM Setting this bit to "1" selects the TrueIDE mode. In
this mode address line A11 is used to switch the
PCE1 and PCE2 memory areas. It is not possible to
use the memory mode.
DMAEN This bit enables the optional DMA mode.
DMA0 This bit configures the available DMA channel
(only channel 0 is possible in conjunction
phyCORE-PXA270).
IDE control register 2 includes the control signals for reset and ready.
The hard drive reset can be controlled via software. Bit 1 of the IDE
control register 2 will generate a reset if set to "0" while setting this bit
to "1" will end the reset cycle. Reading bit 3 returns the status of the
hard drive's RDY signal.
REG ADDR D7 D3 D2 D1 D0
IDE 2 0x20001004 Res RDY Res IDE_RES RES
RW R/W=0 R R/W=0 R/W=0 R=1
xIDE_RDY x/IDE_RES
Table 22: IDE Control Register 2
IDE_RES High active reset signal for the hard drive.
/RDY Shows current state of the hard drive's ready signal.