Phytec phyCORE-PXA270, Hardware Manual

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Carrier Board phyCORE-PXA270
Before entering DeepSleep Mode is it important to render the
SDRAM into self-refresh mode and to ensure that VBAT is available
to supply the device internally. If the system "wakes up" and resumes
full operation it will continue to excecute at the same stage where it
was before going into DeepSleep Mode. Power consumption during
this mode is in the lower milliampere range.
For better support of this function improvements in the board's VBAT
support circuitry were made on PCB revision 1220.3. VBAT is now
created by a 3.1 V linear regulator. Power can be supplied from three
different sources. If the DC input voltage is supplied from a wall
adapter it will first be converted down by a 5 V linear regulator and a
gold cap is charged simultaneoulsy. This voltage then supplies the
3.1 V linear voltage regulator for VBAT. In the absense of the DC
input voltage power is supplied by the battery. If neither the DC input
nor the battery voltage are available then the gold cap can buffer the
VBAT supply for 20 minutes while the battery is changed or the DC
input is restored. Jumper J35 can be used to monitor VBAT via
LED
D31. If VBAT is present the LED will illuminate. It is
recommended to leave J35 open (disconnect the LED) because power
consumption of the LED is relatively high.
3.1V Supply
5V Supply
Gold-Cap
VBAT
Vakku
Figure 11: VBAT Supply
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PHYTEC Meßtechnik GmbH 2006 L-668e_1