Phytec phyCORE-PXA270, Hardware Manual, Page: 84 / 114

Carrier Board phyCORE-PXA270
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PHYTEC Meßtechnik GmbH 2006 L-668e_1
Pin Number Signal I/O Comments
Pin Row X17A
1A CLKIN I Optional external clock input of the
processor
2A, 7A, 12A,
17A, 22A, 27A,
32A, 37A, 42A,
47A, 52A, 57A,
62A, 67A, 72A,
77A
GND - Ground 0 V
3A CLK_REQ I/O Indicates Clocksource
4A GPIO0 I/O Processor I/O port,
alternative: interrupt
5A x/CS_2 I/O Freely available /CS signal of the processor,
alternative: GPIO78
6A
x/CS_4
I/O Chip Select signal of the processor,
alternative: GPIO80
8A
x/WE
O Write-enable signal for SDRAM, SRAM
and Flash devices. Please note that the /PWE
signal must be used for I/O components.
9A, 10A, 11A,
13A, 14A, 15A,
16A, 18A,
24A, 25A,
26A, 28A,
36A
xA1, xA2, xA4,
xA7, xA9, xA10,
xA12, xA15,
xA17, xA18,
xA20, xA23,
xA24
I/O Address lines
19A, 20A, 21A,
23A, 29A, 30A,
31A, 33A,
38A, 39A,
40A, 41A,
43A, 44A,
45A, 46A
xD1, xD2, xD4,
xD7, xD9, xD10,
xD12, xD15,
xD18, xD19,
xD20, xD22,
xD25, xD27,
xD28, xD30
I/O Data lines
34A,
35A
xDQM_1,
xDQM_2
O Byte enable signals
48A xRDY I/O Ready signal of the processor,
alternative: GPIO 18
49A xRDnWR O Bus control singal of the processor