Phytec phyCORE-PXA270, Hardware Manual

Page: 87 / 114

GPIO Expansion Interface
©
PHYTEC Meßtechnik GmbH 2006 L-668e_1
79
Pin Number Signal I/O Comments
Pin Row X17B
57B x/SDCAS O /SDCAS control signal for SDRAM
58B
x/PSKSEL
I/O Card0/1 select
alternative: GPIO 79
60B x/PWE I/O PCMCIA memory write signal and I/O
write signal
alternative: GPIO 49
61B x/POE I/O PCMCIA memory read signal
alternative: GPIO 48
62B x/PIOR I/O PCMCIA I/O read signal
alternative: GPIO 50
63B x/PIOW I/O PCMCIA I/O write signal
alternative: GPIO 51
65B /LAN_IRQ I/O Interrupt LAN controller
66B L_CS O LCD CS
alternative: GPIO 19
67B L_DD16 O LCD data
alternative: GPIO 86
68B L_DD17 O LCD data
alternative: GPIO 87
70B, 71B,
72B, 73B,
75B, 76B
77B, 78B
80B
L_DD0, L_DD1,
L_DD2, L_DD4,
L_DD7, L_DD9,
L_DD10, L_DD12,
L_DD15
I/O LCD data bus
alternative: GPIO 58, GPIO 59, GPIO 60,
GPIO 65, GPIO 67, GPIO 68, GPIO 70,
GPIO 73
Pin Row X17C
1C, 2C +3V3 P Supply v3.3 VDC
3C, 7C, 12C,
17C, 22C, 27C,
32C, 37C, 42C,
47C, 52C, 57C,
62C, 67C 72C,
77C
GND P Ground 0 V
4C VMMC P Optional supply voltage for internal MMC
card
5C VBAT P Input for external battery
6C VCC_LCD P VCC for LCD Port
8C USB_H_PWR P Over-current indicator from ports 3, 2 and 1
9C USIM_VCC P VCC (3.0 V or 1.8 V) USIM
10C /RESIN I/O /Reset input for reset controller at U9
11C /RESET_OUT I/O /Reset output of the PXA270 processor
13C NSSP_TxD I/O Network SPI TxD signal, used for CAN
Controller
Alternative: GPIO 81