Memory
Configuration
©
PHYTEC Meßtechnik GmbH 2006 L-668e_1
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5
Memory Configuration
The Carrier Board for the phyCORE-PXA270 uses the module's /CS1
and /CS2 signals as well as the PCMCIA interface for controlling the
components on the data bus. All other /CS and /SDCS signals from the
phyCORE-PXA270 are routed to and can be controlled by the address
decoder (control PLD U7) in order to connect the external data bus
drivers and allow for custom-specific modification options. The
PCMCIA interface is managed by the second address decoder
(Control PLD U6), which generates all necessary signals for the CF
card and the IDE interface.
/CS0
2 * 16-bit Flash memory 16 to 64 MByte asynchronous /
synchronous (optional 16-bit Flash memory 8 MByte
asynchronous)
/CS1
16-bit VLIO interface, address decoder U7 on the Carrier
Board
/CS2
16-bit VLIO interface, expansion connector X17 on the
Carrier Board
/CS3
Used for PSKSEL (PC Card Socket Select)
/CS4
free 16-bit VLIO interface
/CS5
Ethernet chip with 32-bit VLIO interface on the
phyCORE-PXA270 module
The SDRAM /CS signals extend to the Carrier Board's X-Bus
connector X17. Depending on the phyCORE-PXA270 configuration
option, these /CS signals /SDCS_0 through /SDCS_3 are connected
with the chips of both SDRAM banks.
/SDCS_0
64 MB 2*16-bit SDRAM on the phyCORE-PXA270
/SDCS_1 optional 64 MB 2*16-bit SDRAM on the
phyCORE-PXA270
/SDCS0/1 optional 128 MB 2*16-bit SDRAM on the
phyCORE-PXA270 (applicable when using SDRAM
with two /CS signals per chip)
/SDCS2/3 optional 128 MB 2*16-bit SDRAM on the
phyCORE-PXA270 (applicable when using SDRAM
with two /CS signals per chip)
Summary of Contents for phyCORE-PXA270
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