Phytec phyCORE-PXA270, Hardware Manual, Page: 85 / 114

GPIO Expansion Interface
©
PHYTEC Meßtechnik GmbH 2006 L-668e_1
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Pin Number Signal I/O Comments
Pin Row X17A
50A,
51A
xDREQ_0
xDVAL_0
O DMA request singal
DREQ0
alternative: GPIO 115
DVAL0 alternative: GPIO 116
53A, x/SDCKE_0 O Clock enable for synchronous memory
55A,
56A
x/SDCLK_0
x/SDCLK_1
O Clock signal for synchronous memory
58A,
59A
x/PCE_1
x/PCE_2
I/O PCMCIA Chip Select resp. byte control
signal,
alternative: GPIO85/54
60A x/PWAIT I/O PCMCIA wait signal,
alternative: GPIO56
61A x/IOIS16 I/O PCMCIA 16-bit access
alternative: GPIO57
63A x/PREG I/O PCMCIA register control signal
alternative: GPIO55
64A /LAN_CS I I/O Chip Select for LAN controller
65A /LAN_DATA I DATA Chip Select for LAN controller
66A L_VSYNC O Refresh sync signal from the LCD panel
with internal frame buffer
alternative: GPIO14
68A L_PCLK I/O LCD pixel clock
alternative: GPIO76
69A L_LCLK I/O LCD line clock
alternative: GPIO75
70A L_FCLK I/O LCD frame clock
alternative: GPIO74
71A L_BIAS I/O LCD enable
alternative: GPIO77
73A, 74A,
75A, 76A,
78A,
79A,
80A
L_DD3, L_DD5
L_DD6, L_DD8,
L_DD11,
L_DD13
L_DD14
I/O LCD data
alternative: GPIO61, GPIO63, GPIO64,
GPIO66, GPIO69, GPIO71, GPIO72