Phytec phyCORE-PXA270, Hardware Manual

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Memory Configuration
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PHYTEC Meßtechnik GmbH 2006 L-668e_1
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Control register 8 controls the RS-232 transceiver for the BT/IR
UART and the FF-UART.
REG ADDR D7-D4 D3 D2 D1 D0
CTRL 8 0x04000010 Res BT_Rx FF_RI BT_SD FF_SD
RW R/W=0 R/W R/W R/W R/W
Signal
Name BT_RX_D
ETECT FF_RI_DE
TECT BT_/SHDN FF_/SHDN
Table 15: PLD U7 Control Register 8
FF-SD Setting this bit shuts down the RS-232 transceiver
for the FF-UART.
BT-SD Setting this bit shuts down the RS-232 transceiver
for the BT-UART and IR-UART.
FF_RI If the RS-232 transceiver for the FF-UART is in
power down mode then this bit returns an active RI
signal.
BT_Rx If the RS-232 transceiver for the BT-UART or
IR-UART is in power down mode then this bit
returns an active RxD signal.
The Flash device on the phyCORE module and the AC97 expansion
interface can be configured in control register 9. If /FL_DIS is set to 0,
then it is possible to boot from an external Flash (not the Flash
populating the phyCORE-PXA270).
However it is important to be aware of the bus configuration on the
phyCORE module. When setting the bit FL_WP the Flash will be
write-protected with WP.