Phytec phyCORE-PXA270, Hardware Manual

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GPIO Expansion Interface
©
PHYTEC Meßtechnik GmbH 2006 L-668e_1
83
Pin Number Signal I/O Comments
Pin Row X17D
55D, 56D,
57D, 58D,
60D,
61D,
62D,
63D,
65D,
66D,
67D,
68D,
70D
EGPIO2, EGPIO4,
EGPIO5, EGPIO7
EGPIO10,
EGPIO12,
EGPIO13,
EGPIO15,
EGPIO19,
EGPIO20,
EGPIO21,
EGPIO23,
EGPIO26
I/O Additional GPIOs generated by the
MAX7301 IC with 7 interrupt-capable
inputs for connection to a matrix keyboard
71D SSP_EXTCLK I SPI external clock
alternative: GPIO 27
72D SSP_CLK O SPI clock signal
alternative: GPIO 23
73D SSP_SFRM I/O SPI frame signal
alternative: GPIO 24
75D FL_DIS I Signal to disable internal Flash
76D SSP_SYSCLK I/O SYSCLOCK SSP
Alternative: GPIO 53
77D PWR_SDA I/O Power I2C Serial Data/Address signal
Alternative: GPIO 4
78D PWR_SCL O Power I2C Serial Clock Line signal
Alternative: GPIO 3
80D /INT_RTC O Interrupt output RTC
Table 53: GPIO Expansion Bus X17 Pin Assignment
The pin assignment on the phyCORE-PXA270, in conjunction with
the expansion bus (X17) on the Carrier Board and the patch field on
an expansion board, is as follows: