PCM-061/phyCORE-i.MX7 System on Module
L-821e_2
© PHYTEC America L.L.C. 2017
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4.3.1
Power Domains
As stated before, the SOM has two input voltage rails and two output rails. The VCC_SOM input rail provides power to the
PMIC, which then generates other voltage rails on the SOM. A load switch IC at U13 is used to generate the 3.3V rails used
on the phyCORE-i.MX7 (VLDO3_3V3, NVCC_3V3, and 3V3MEM_IN) from VCC_SOM. This load switch is enabled by the
PMIC to ensure proper power sequencing for all on-board supplies. VCC_SOM is also switched to supply the SD1 power
rail NVCC_SD1 through a FET enabled by the PMIC. Refer to
Table 5
below for descriptions of all of the external power
supplies at the phyCORE connector.
The following tables summarize the relationships between the voltage rails and the devices on the phyCORE-i.MX7.
Table 5. External Supply Voltages
Signal
Description
Direction Function
VCC_SOM
3.3V system power supply
IN
PMIC Power Supply
VBAT
3.0V RTC battery supply
IN
Backup power for RTC U19
VLDO2_1V5
1.5V power supply
OUT
Power rail for Mini-PCIe on Carrier Board
SW2_1V8
1.8V power supply
OUT
Reference output for sequencing
Table 6. Internal Voltage Rails
Device
Device Output
Schematic Signal
Voltage Function
PMIC
U3
VLDO1
VLDO1_1V8
1.8
i.MX7 LPSR Domain Supply
VLDO2
VLDO2_1V5
1.5
i.MX7 Carrier Board Mini-PCIe Supply
VSNVS
VSNVS
3.0
i.MX7 SNVS Domain Supply
SW1A
VDD_ARM_IN
1.1
i.MX7 Core Supply Voltage
SW1B
VDD_SOC_IN
1.0
i.MX7 Core Supply Voltage
SW2
SW2_1V8 / NVCC_1V8
1.8
ADC Supply / Supply for NVCC_SD2 and
NVCC_SD3 / i.MX7 power for analog domain
and LDOs
SW3
SW3_1V35 / NVCC_DRAM
1.35
DDR Supply Voltage
Load Switch
U13
VOUT
VCC_3V3_S3
3.3
Multiple component voltage supply
Switching
FET Q2
VOUT
VCC_3V3_S4
3.3
SD1 VCC
4.3.2
Power Management
The PMIC provides an input signal to control the power state of the system by generating a turn-on event. This signal is
provided as X_PMIC_PWRON, and can be used to bring the PMIC out of OFF and Sleep modes into the ON mode. By
default, X_PMIC_PWRON is pulled up to the VSNVS rail on the SOM. Therefore, it is recommended to implement an open-
drain output to drive X_PMIC_PWRON externally. Refer to the PMIC datasheet for information on how to configure the
PWRON pin.
X_3V3MEM_EN is provided as an output at the phyCORE connector to sequence an external 3.3V power rail to match the
timing of VCC_3V3_S3. It is recommended to use a load switch with similar characteristics as U13 on the SOM (TPS22965)
so that the external 3.3V rail is sequenced as close as possible to the internal VCC_3V3_S3 rail. This is intended for
sequencing power before the release of POR. It is recommended to use this power sequencing for configuring the boot
signals on a carrier board (as these are strapped at the release of POR) and supplying memory devices (i.e. SD card).
