PCM-061/phyCORE-i.MX7 System on Module
L-821e_2
© PHYTEC America L.L.C. 2017
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9
Serial Interfaces
The i.MX7 provides numerous serial interfaces, some of which are provided with an on-board transceiver for direct
connection to external devices. Only a subset of the interfaces are brought out of the phyCORE connector as the phyCORE-
i.MX7 default multiplexing configuration. The following sections describe the default interfaces on the phyCORE-i.MX7.
Additional interfaces can be accessed through alternate muxing configurations. Please refer to NXP
’s technical reference
manual for more information on pin muxing options.
9.1
USB
The phyCORE-i.MX7 provides two USB 2.0 OTG interfaces with integrated USB PHYs. Typically, an external USB connector
is all that is needed for USB functionality. However, USB power switch circuits can be implemented on a baseboard to add
additional VBUS enable and over-current detection functionality.
An additional HSIC USB 2.0 port is available with an integrated HSIC USB PHY.
9.2
Ethernet
The phyCORE-i.MX7 can connect to a LAN via the i.MX7 embedded 10/100/1000 Ethernet switch. The Ethernet switch has
two ports: Ethernet1 and Ethernet2. Both ports provide MII/RMII/RGMII signals from the processor and require an
external Ethernet PHY for connection to a physical network. The SOM provides the option of an Ethernet PHY on
Ethernet1, but not on Ethernet2. Ethernet2 is only available at the phyCORE-Connector via the MII/RMII/RGMII signals.
9.2.1
Ethernet1
The phyCORE-i.MX7 can be populated with a 10/100/1000Base-T Ethernet transceiver PHY at U8, allowing direct
connection to an RJ-45 connector with integrated magnetics. See
Table 3
for the locations of the Ethernet1 signals on the
phyCORE-Connector. All Ethernet1 signals are labeled as X_ETH1
… on the connector.
The KSZ9031 transceiver supports HP Auto MDIX technology, eliminating the need for the consideration of a direct connect
LAN cable, or a cross over patch cable.
Special routing, layout, and other circuit design considerations should be followed by referencing the phyCORE-i.MX7
Carrier Board schematics.
CAUTION:
Please reference the KSZ9031 Ethernet Controller datasheet when designing the Ethernet transformer circuitry.
9.2.2
Ethernet2
The i.MX7 Ethernet2 interface signals can connect to any industry standard Ethernet transceiver or configured for other
multiplex functionality. The i.MX7 supports MII, RMII, and RGMII modes on the interface. GMII is not supported by the
processor.
It is strongly recommended to place the Ethernet PHY on the Carrier Board as close as possible to the RGMII2 pins at the
phyCORE connector to achieve a trace length of less than 100mm. Please refer to the datasheet of the chosen Ethernet
transceiver for more information regarding signal timings. Additional routing, layout, and other circuit design
considerations should be followed by referencing the phyCORE-i.MX7 Carrier Board schematics.
For signal integrity purposes, source termination resistors are placed on the output signals of the RGMII2 interface on the
SOM.
