Phytec phycore i.mx7 Hardware Manual Download Page 20

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PCM-061/phyCORE-i.MX7 System on Module

L-821e_2

X1, Column A

Pin #

Signal

Type

Level

Description

A46

X_SD1_CD_B

3.3V

SD/MMC1 Card Detect

A47

X_SD1_WP

3.3V

SD/MMC1 Write Protect

A48

X_SD1_CLK

3.3V

SD/MMC1 Clock

A49

X_SD1_CMD

3.3V

SD/MMC1 Command

A50

GND

Ground

A51

X_SD1_DATA0

3.3V

SD/MMC1 Data 0

A52

X_SD1_DATA1

3.3V

SD/MMC1 Data 1

A53

X_SD1_DATA2

3.3V

SD/MMC1 Data 2

A54

X_SD1_DATA3

3.3V

SD/MMC1 Data 3

A55

GND

Ground

A56

VCC_SOM

PWR

3.3V

3.3V Input Power

A57

VCC_SOM

PWR

3.3V

3.3V Input Power

A58

VCC_SOM

PWR

3.3V

3.3V Input Power

A59

VCC_SOM

PWR

3.3V

3.3V Input Power

A60

GND

Ground

X1, Column B

Pin #

Signal

Type

Level

Description

X_GPIO2_12

3.3V

i.MX7 GPIO2_12

X_GPIO2_13

3.3V

i.MX7 GPIO2_13

X_GPIO2_14

3.3V

i.MX7 GPIO2_14

X_GPIO2_15

3.3V

i.MX7 GPIO2_15

GND

Ground

X_MX7_ONOFF

i.MX7 ON/OFF Input (

Drive using an open drain output

)

X_3V3MEM_EN

OUT

3.3V

External 3.3V Sequencing Output

X_PMIC_PWRON

PMIC PWRON Input

X_POR_B

OUT

3.3V

Power On Reset

B10

GND

Ground

B11

X_GPIO1_09

3.3V

i.MX7 GPI1_09

B12

X_SNVS_TAMPER2

1.8V

Tamper Detection Pin 2

B13

SW2_1V8

PWR

1.8V

1.8V Output

B14

GND

Ground

B15

X_UART1_RX

3.3V

UART1 Receive

B16

X_UART1_TX

OUT

3.3V

UART1 Transmit

B17

X_UART2_RX

3.3V

UART2 Receive

B18

X_UART2_TX

OUT

3.3V

UART2 Transmit

B19

X_UART3_RX

3.3V

UART3 Receive

B20

X_UART3_TX

OUT

3.3V

UART3 Transmit

B21

GND

Ground

B22

X_PCIE_RX_N

DIFF100

PCIe Differential Negative Receive

B23

X_PCIE_RX_P

DIFF100

PCIe Differential Positive Receive

B24

GND

Ground

B25

X_PCIE_TX_P

DIFF100

PCIe Differential Positive Transmit

B26

X_PCIE_TX_N

DIFF100

PCIe Differential Negative Transmit

B27

GND

Ground

B28

X_PCIE_REFCLK_P

DIFF100

PCIe Differential Positive Reference Clock

Summary of Contents for phycore i.mx7

Page 1: ...A product of a PHYTEC Technology Holding company ...

Page 2: ...e use of this manual or its associated product PHYTEC America L L C reserves the right to alter the information contained herein without prior notification and accepts no responsibility for any damages which might result Additionally PHYTEC America L L C offers no guarantee nor accepts any liability for damages arising from the improper usage or improper installation of the hardware or software PH...

Page 3: ...C_SOM 27 4 2 Power Mode Management 27 4 3 Power Management IC U2 28 5 Real Time Clock RTC 31 5 1 i MX7 RTC 31 5 2 External RTC 31 6 System Configuration and Booting 32 6 1 Boot Mode Pin Settings 32 6 2 Boot Device Selection 32 6 3 Boot Device Configuration 33 7 System Memory 34 7 1 DDR3 SDRAM U3 U4 34 7 2 eMMC U5 and NAND Flash U6 Memory 34 7 3 I2 C EEPROM U11 34 7 4 QSPI NOR Flash Memory U9 35 7 ...

Page 4: ...n Module L 821e_2 PHYTEC America L L C 2017 4 11 Technical Specifications 40 12 Hints for Integrating and Handling the phyCORE i MX7 42 12 1 Integrating the phyCORE i MX7 42 12 2 Handling the phyCORE i MX7 42 13 Revision History 43 ...

Page 5: ...am 14 Figure 2 phyCORE i MX7 Component Placement top view 15 Figure 3 phyCORE i MX7 Component Placement bottom view 16 Figure 4 Pinout of the phyCORE Connector top view with cross section insert 18 Figure 5 Jumper Numbering Schemes 25 Figure 6 Power Supply Diagram 28 Figure 7 phyCORE i MX7 Mechanical Dimensions profile view 40 ...

Page 6: ... Descriptions and Settings 26 Table 5 External Supply Voltages 29 Table 6 Internal Voltage Rails 29 Table 7 Typical VBAT Power Consumption 31 Table 8 Boot Mode Configuration 32 Table 9 Boot Device Selection 32 Table 10 SD MMC Boot Configuration Description 33 Table 11 I2C1 Reserved Addresses 38 Table 12 Technical Specifications 41 Table 13 Recommended Operating Conditions for the Input and Output ...

Page 7: ...ed in this manual are as follows Signals that are preceded by an n or character e g nRD RD or RD or that have a dash on top of the signal name e g RD are designated as active low signals That is their active state is when they are driven low or are driving low A 0 indicates a logic zero or low level signal while a 1 represents a logic one or high level signal The hex numbers given for addresses of...

Page 8: ...n Module Used in reference to the PCM 061 phyCORE i MX7 System on Module VBAT SOM standby voltage input Different types of signals are brought out at the phyCORE Connector The following table lists the abbreviations used to specify each type of signal Table 2 Types of Signals Type of Signal Description Abbr Power Supply voltage PWR Ref Voltage Reference voltage REF USB Power USB voltage USB Input ...

Page 9: ...XP i MX7 processor can be found in the processor datasheet and or technical reference manual TRM Ordering Information The part numbering of the phyCORE i MX7 has the following structure1 1 This structure shows the ordering options available as of the printing of this manual Additional ordering options may have been added Please contact our sales team to check current availability inventory and lea...

Page 10: ... interface to a host PC NOTE Implementation of PHYTEC products into target devices as well as user modifications and extensions of PHYTEC products is subject to renewed establishment of conformity to and certification of Electro Magnetic Directives Users should ensure conformance following any modifications to the products as well as implementation of the products into target systems The phyCORE i...

Page 11: ...as been established to fulfill our philosophy Avoidance Strategies Avoid changes by evaluating longevity of a parts during design in phase Ensure availability of equivalent second source parts Maintain close contact with part vendors for awareness of roadmap strategies Change Management in Case of Functional Changes Avoid impacts on Product functionality by choosing equivalent replacement parts Av...

Page 12: ... x 50 mm insert ready System on Module populated with the NXP i MX7 microcontroller Its universal design enables its insertion in a wide range of embedded applications All controller signals and ports extend from the controller to high density pitch 0 5 mm connectors aligning two sides of the board allowing it to be inserted like a big chip into a target application Precise specifications for the ...

Page 13: ...rica L L C 2017 13 6x UART2 2x eCSPI2 3x SDIO SD MMC 2x CAN PCI Express 2 0 1 Lane MIPI CSI 2 Lane MIPI DSI 2 Lane 4x ADC 3x Tamper 3x PWM2 1x SAI2 1x QSPI Keypad 3x3 2 JTAG GPIO 2 Highly multiplexed All ports may not be available at once depending on use case ...

Page 14: ...PCM 061 phyCORE i MX7 System on Module L 821e_2 PHYTEC America L L C 2017 14 1 1 Block Diagram Figure 1 phyCORE i MX7 Block Diagram ...

Page 15: ...odule L 821e_2 PHYTEC America L L C 2017 15 1 2 Component Placement Diagram Figure 2 phyCORE i MX7 Component Placement top view 3 3 Detailed component placement diagrams with all reference designators are available through our website ...

Page 16: ...PCM 061 phyCORE i MX7 System on Module L 821e_2 PHYTEC America L L C 2017 16 Figure 3 phyCORE i MX7 Component Placement bottom view 3 ...

Page 17: ...example is located in the lower right hand corner of the matrix looking down through the top of the SOM The pin numbering values decrease moving down on the board Lettering of the pin connector columns progresses alphabetically from right to left for each connector refer to Figure 4 The numbered matrix can be aligned with the phyCORE i MX7 viewed from above phyCORE Connector pointing down or with ...

Page 18: ...descriptions in Table 3 however are in regard to the specification of the phyCORE i MX7 and the functions defined therein Please refer to the i MX7 datasheet or the schematic to learn about alternative functions In order to utilize a specific pin s alternative function the corresponding registers must be configured within the appropriate driver of the BSP To support all features of the phyCORE i M...

Page 19: ...TX OUT 3 3V CAN2 Transmit A20 GND Ground A21 X_UART6_RX IN 3 3V UART6 Receive A22 X_UART6_TX OUT 3 3V UART6 Transmit A23 X_UART5_RX IN 3 3V UART5 Receive A24 X_UART5_TX OUT 3 3V UART5 Transmit A25 GND Ground A26 X_NAND_CE1_B OUT 3 3V NAND Chip Enable 1 A27 X_NAND_CE0_B OUT 3 3V NAND Chip Enable 0 A28 X_NAND_DQS IO 3 3V NAND DQS Signal A29 X_NAND_READY_B IO 3 3V NAND Ready Signal A30 X_NAND_CE2_B O...

Page 20: ...2_14 B4 X_GPIO2_15 IO 3 3V i MX7 GPIO2_15 B5 GND Ground B6 X_MX7_ONOFF IN 3V i MX7 ON OFF Input Drive using an open drain output B7 X_3V3MEM_EN OUT 3 3V External 3 3V Sequencing Output B8 X_PMIC_PWRON IN 3V PMIC PWRON Input B9 X_POR_B OUT 3 3V Power On Reset B10 GND Ground B11 X_GPIO1_09 IO 3 3V i MX7 GPI1_09 B12 X_SNVS_TAMPER2 IN 1 8V Tamper Detection Pin 2 B13 SW2_1V8 PWR 1 8V 1 8V Output B14 GN...

Page 21: ... B42 GND Ground B43 X_SPI1_SCLK IO 1 8V 3 3V4 SPI1 Clock B44 X_SPI1_MISO IO 1 8V 3 3V4 SPI1 Master In Slave Out B45 X_SPI1_MOSI IO 1 8V 3 3V4 SPI1 Master Out Slave In B46 X_SPI1_SS0 IO 1 8V 3 3V4 SPI1 Slave Select 0 B47 X_nWDOG_RST OUT 3 3V Active Low Soft Reset Signal B48 GND Ground B49 X_UART7_RX IN 1 8V 3 3V4 UART7 Receive B50 X_UART7_RTS OUT 1 8V 3 3V4 UART7 Request to Send B51 X_UART7_TX OUT ...

Page 22: ...ATA23_BOOT23 IO 3 3V LCD1 Display Data 23 BOOT 23 Signal A21 X_LCD1_DATA1_BOOT1 IO 3 3V LCD1 Display Data 1 BOOT 1 Signal A22 X_LCD1_DATA22_BOOT22 IO 3 3V LCD1 Display Data 22 BOOT 22 Signal A23 GND Ground A24 X_LCD1_DATA2_BOOT2 IO 3 3V LCD1 Display Data 2 BOOT 2 Signal A25 X_LCD1_DATA5_BOOT5 IO 3 3V LCD1 Display Data 5 BOOT 5 Signal A26 X_LCD1_DATA4_BOOT4 IO 3 3V LCD1 Display Data 4 BOOT 4 Signal...

Page 23: ...5 GND Ground B6 X_ETH1_B RGMII1_TX0 OUT 3 3V ETH1 Differential Negative B RGMII1 Transmit Data 0 B7 X_ETH1_B RGMII1_TX1 OUT 3 3V ETH1 Differential Positive B RGMII1 Transmit Data 1 B8 X_ETH1_A RGMII1_TX2 OUT 3 3V ETH1 Differential Negative A RGMII1 Transmit Data 2 B9 X_ETH1_A RGMII1_TX3 OUT 3 3V ETH1 Differential Positive B RGMII1 Transmit Data 3 B10 GND Ground B11 X_RGMII1_TXC OUT 3 3V RGMII1 Tra...

Page 24: ...V USB1 Differential Data Negative B42 GND Ground B43 X_USB_OTG1_ID IN 3 3V USB1 ID Signal B44 X_USB_OTG1_VBUS PWR 5V USB1 Power B45 X_USB_OTG2_ID IN 3 3V USB2 ID Signal B46 X_USB_OTG2_VBUS PWR 5V USB Power B47 GND Ground B48 X_USB_OTG2_OC IN 3 3V USB2 Overcurrent Detection B49 X_USB_OTG2_PWR OUT 3 3V USB2 Control Signal to Enable VBUS Power B50 X_USB_OTG1_OC IN 3 3V USB1 Overcurrent Detection B51 ...

Page 25: ...ring Overheating the board can cause the solder pads to loosen rendering the module inoperable Carefully heat neighboring connections in pairs After a few alternations components can be removed with the solder iron tip Alternatively a hot air gun can be used to heat and loosen the bonds Figure 5 Jumper Numbering Schemes The bold items in Table 4 below represent the default configuration for each j...

Page 26: ... operates at 1 8V SD3 operate at 3 3V required for NAND population J23 1 2 2 3 SD2 operates at 1 8V SD2 operate at 3 3V J24 1 2 2 3 2 4 External RTC interrupt is routed to a GPIO2_04 EPDC1_DATA04 at the processor External RTC interrupt is routed to the X_MX7_ONOFF signal to be used as a wake signal External RTC interrupt is routed to the PMIC PWRON pin to be used to trigger a PMIC power on event J...

Page 27: ... GND pins For the best EMI performance it is recommended to connect ALL ground pins at the phyCORE Connector X1 X2 to a solid ground plane At the very least a matching number of ground pins to power pins should be made in addition to using the ground pins surrounding signals used in application circuitry Please refer to Table 3 for the locations of all ground pins on the phyCORE Connector The foll...

Page 28: ...ower Management IC U2 The phyCORE i MX7 provides an on board Power Management IC PMIC NXP PF3000 at position U2 to generate the voltages required by the processor and on board components Figure 6 presents a graphical depiction of the SOM powering scheme Figure 6 Power Supply Diagram ...

Page 29: ...X7 Carrier Board Mini PCIe Supply VSNVS VSNVS 3 0 i MX7 SNVS Domain Supply SW1A VDD_ARM_IN 1 1 i MX7 Core Supply Voltage SW1B VDD_SOC_IN 1 0 i MX7 Core Supply Voltage SW2 SW2_1V8 NVCC_1V8 1 8 ADC Supply Supply for NVCC_SD2 and NVCC_SD3 i MX7 power for analog domain and LDOs SW3 SW3_1V35 NVCC_DRAM 1 35 DDR Supply Voltage Load Switch U13 VOUT VCC_3V3_S3 3 3 Multiple component voltage supply Switchin...

Page 30: ...pin The VBAT rail also supplies the LICELL pin on the PMIC allowing for the connection of a coin cell backup battery or super capacitor If VCC_SOM goes below the VIN threshold of the PMIC or is removed the VBAT voltage supplied to the LICELL pin will be switched to maintain power for the internal logic and the VSNVS rail If VBAT is not present or disconnected then the memory will be cleared and VS...

Page 31: ...ed to the I2C1 bus at address 0x68 The external RTC uses less power than the i MX7 internal RTC and can be used when very low battery power is critical The external RTC typically uses 350nA at 3V In order for the external RTC to maintain time when main system power is removed the VBAT input must be supplied with power To achieve the lowest power consumption resistor R172 must be removed to disconn...

Page 32: ...dify the default boot configuration on a Carrier Board it is recommended to use 1k pull up or pull down resistors to override the SOM settings Please note that after booting up these signals are used to transmit data via the LCD1 display interface For more information about pad multiplexing configuration please refer to NXP i MX7 Technical Reference Manual 6 1 Boot Mode Pin Settings Table 8 descri...

Page 33: ...OOT_CFG Latching Signal Definition Setting X_LCD1_DATA 15 12 _BOOT 15 12 Boot Device Selection 0001 SD eSD SDXC 0010 MMC eMMC X_LCD1_DATA 11 10 _BOOT 11 10 SD Port Selection 00 USDHC 1 01 USDHC 2 10 USDHC 3 X_LCD1_DATA 9 _BOOT 9 SD Power Cycle Enable 0 Disabled 1 Enabled X_LCD1_DATA 8 _BOOT 8 Loopback Clock Selection 0 Through SD Pad 1 Direct X_LCD1_DATA 7 _BOOT 7 Fast Boot Support 0 Normal Boot 1...

Page 34: ... an operating system or boot loader SDRAM must be initialized through the appropriate SDRAM configuration registers on the i MX7 controller Refer to the i MX7 Technical Reference Manual about accessing and configuring these registers 7 2 eMMC U5 and NAND Flash U6 Memory The phyCORE i MX7 can be populated with either an eMMC or NAND flash as an easy to program nonvolatile memory solution The phyCOR...

Page 35: ...ll RTOS Using a SPI Flash can eliminate the need to install NAND Flash or eMMC memory on the SOM This could reduce BOM costs free up the NAND signals for other muxing options and remove the need for the bad block management that is required when using NAND Flash 7 5 Memory Model There is no special address decoding device on the phyCORE i MX7 therefore the memory model is given according to the me...

Page 36: ...provided at the phyCORE connector directly from the processor These two ports allow support for external SD MMC devices such as an SD card or a WiFi Blueooth module and are provided with 22 Ohm source termination resistors on the SOM The SD MMC3 interface is used to interface with an on board flash device either eMMC at U5 or NAND at U6 depending on the SOM configuration see Section 7 2 ...

Page 37: ... phyCORE Connector via the MII RMII RGMII signals 9 2 1 Ethernet1 The phyCORE i MX7 can be populated with a 10 100 1000Base T Ethernet transceiver PHY at U8 allowing direct connection to an RJ 45 connector with integrated magnetics See Table 3 for the locations of the Ethernet1 signals on the phyCORE Connector All Ethernet1 signals are labeled as X_ETH1 on the connector The KSZ9031 transceiver sup...

Page 38: ...ng a data rate up to 5Gbps The PCIe reference clock into the processor is provided by an external 100MHz oscillator circuit with HCSL termination Coupling capacitors are not provided on the SOM for the differential TX data signals These TX coupling capacitors should be implemented on a carrier board A 1 5V supply rail VLDO2_1V5 is provided at the phyCORE Connector from the PMIC to support Mini PCI...

Page 39: ...he phyCORE i MX7 is equipped with a JTAG interface for downloading program code into the internal RAM or for debugging programs currently executing The JTAG interface is accessible via the phyCORE Connectors Please reference the NXP documentation for further information regarding the JTAG interface ...

Page 40: ...he tallest component on the bottom excluding the phyCORE connectors The maximum component height excluding connectors X1 and X2 is approximately 1 9 mm on the bottom connector side of the PCB and approximately 2 mm on the top microcontroller side The PCB is approximately 1 5 mm thick The distance from the surface of the Carrier Board to the highest component on the top side of the board is approxi...

Page 41: ...except for Serial RS 232 and SD card 170 mA Measured while testing the following interfaces devices simultaneously via a python test script in Linux ETH1 ETH2 iperf test USB1 USB2 bandwidth test LCD Display RS232 Mini PCIe via StarTech Gigabit ethernet adapter card CAN via PCAN View Memtester RTC EEPROM eMMC SD 730 mA IVLDO2_1V5 1 5V Output load current 250 mA ISW2_1V8 1 8V Output load current Not...

Page 42: ... MX7 Carrier Board schematic reference Schematics are made available upon request phyCORE iMX7 Pins file http develop phytec com display public PRODUCTINFO phyCORE i MX7 Landing 409943289 Phone e mail FAQ wiki and other online support by visiting http phytec com contact 12 2 Handling the phyCORE i MX7 Removal of various components such as the microcontroller and the standard quartz is not advisabl...

Page 43: ...nal Revised explanation of SW2_1V8 to explicitly recommend only using it for external sequencing Fixed table numbering Updated average mass measurement using 4x PCM 061 A4 units 2017 05 24 L 821e_2 Added mechanical dimensions drawing Added reference to pin mux file Revised pin description table Explicitly describe the signals that can be set as either 1 8V or 3 3V Revised Table 4 to include UART7 ...

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