phyCARD-M [PCA-A-M1-xxx]
42
©
PHYTEC Messtechnik GmbH 2010 L-750e_1
8
SD / MMC Card Interfaces
The X-Arc bus features an SD / MMC Card interface. On the
phyCARD-M the interface signals extend from the controllers first
Enhanced Secure Digital Host Controller (SDIO1) to the phyCARD-
Connector.
Table 13
shows the location of the different interface
signals on the phyCARD-Connector. The Secure Digital Host
Controller is fully compatible with the SD Memory Card Specification
2.0 and SD I/O Specification 2.0 with 1 and 4 channel(s) and supports
data rates from 25 Mbps to 200 Mbps (refer to the
i.MX35 Reference
Manual
for more information).
Due to compatibility reasons a card detect signal (X_SDIO_CD) is
added to the SD / MMC Card Interface. This signal connects to port
GPIO3_1 of the i.MX35.
Pin # Signal
I/O SL
Description
X2A3
1
X_SD1_DAT
A0
I/O
VDD_3V3
SD/MMC Data line both in 1-
bit and 4-bit mode
X2A3
2
X_SD1_DAT
A2
I/O
VDD_3V3
SD/MMC Data line both in 1-
bit and 4-bit mode
X2A3
3
X_SD1_CLK O
VDD_3V3 SD/MMC Clock for
MMC/SD/SDIO
X2B3
1
X_SD1_DAT
A1
I/O
VDD_3V3
SD/MMC Data line both in 1-
bit and 4-bit mode
X2B3
2
X_SD1_DAT
A3
I/O
VDD_3V3
SD/MMC Data line both in 1-
bit and 4-bit mode
X2B3
3
X_SD1_CMD O
VDD_3V3 SD/MMC Command for
MMC/SD/SDIO
X2B4
6
X_SDIO_CD I
VDD_3V3
SD/MMC Card Detect for
MMC/SD/SDIO
Table 13:
Location of SD/ MMC Card interface signals