Phytec phyCARD-M Hardware Manual Download Page 114

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phyCARD-M [PCA-A-M1-xxx]

106

PHYTEC Messtechnik GmbH 2010 L-750e_1

Button Setting Description

S3_7/
S3_8

0/0

0/1

1/x

SS0/GPIO0

-> expansion 0 (X8A),

SS1/GPIO1

-> expansion 1 (X9A)

SS0/GPIO0

-> expansion 0 (X8A),

SS1/GPIO1

-> display data connector (X6)

SS0/GPIO0

-> expansion 1 (X9A),

SS1/GPIO1

-> display data connector (X6)

Table 45:

SPI and GPIO connector selection

: GPIO0

≙

GPIO1_1 (at L16) and GPIO1

≙

GPIO2_23 (at V3) of the i.MX35

Summary of Contents for phyCARD-M

Page 1: ...A product of a PHYTEC Technology Holding company phyCARD M Hardware Manual Document No L 750e_1 SBC Prod No PCA A M1 xxx CB Prod No PBA A 01 Edition June 2010 ...

Page 2: ... PHYTEC Messtechnik GmbH offers no guarantee nor accepts any liability for damages arising from the improper usage or improper installation of the hardware or software PHYTEC Messtechnik GmbH further reserves the right to alter the layout and or design of the hardware without prior notification and accepts no liability for doing so Copyright 2010 PHYTEC Messtechnik GmbH D 55129 Mainz Rights includ...

Page 3: ...em Memory 38 7 1 DDR2 SDRAM U8 U11 38 7 2 NAND Flash Memory U13 39 7 3 I C EEPROM U6 39 7 3 1 Setting the EEPROM Lower Address Bits J1 J3 J4 40 7 3 2 EEPROM Write Protection Control J16 41 7 4 Memory Model 41 8 SD MMC Card Interfaces 42 9 Serial Interfaces 44 9 1 Universal Asynchronous Interface 45 9 2 USB OTG Interface 46 9 3 USB Host Interface 47 9 4 Ethernet Interface 48 9 4 1 PHY Physical Laye...

Page 4: ...ivity P1 86 17 3 4 Ethernet Connectivity X10 88 17 3 5 USB Host Connectivity X7 X8 X9 X30 X33 89 17 3 6 USB OTG Connectivity X29 91 17 3 7 Display Touch Connectivity X6 X32 92 17 3 7 1 Display Data Connector X6 93 17 3 7 2 Display Power Connector X32 96 17 3 7 3 Touch Screen Connectivity 97 17 3 8 Camera Interface X5 99 17 3 9 Audio Interface X1 X2 X3 101 17 3 10 I2 C Connectivity 102 17 3 11 SPI ...

Page 5: ...l dimensions 61 Figure 12 phyCARD M component placement top view 64 Figure 13 phyCARD M component placement bottom view 65 Figure 14 phyBASE phyCARD M Carrier Board 69 Figure 15 phyBASE Overview of Connectors LEDs and Buttons 70 Figure 16 Typical jumper numbering scheme 78 Figure 17 phyBASE jumper locations 79 Figure 18 phyCARD M SBC Connectivity to the Carrier Board 82 Figure 19 Power adapter 83 ...

Page 6: ... connectors X5 99 Figure 28 Audio interface at connectors X1 X2 X3 101 Figure 29 Expansion connector X8A X9A 105 Figure 30 SD Card interface at connector X26 108 Figure 31 Boot Mode Selection Jumper JP1 109 Figure 32 System Reset Button S1 111 Figure 33 Carrier Board Physical Dimensions 114 ...

Page 7: ...le 12 EEPROM write protection states via J16 41 Table 13 Location of SD MMC Card interface signals 42 Table 14 Location of the UART signals 45 Table 15 Location of the USB OTG signals 46 Table 16 Location of the USB Host signals 47 Table 17 Location of the Ethernet signals 48 Table 18 Fast Ethernet controller memory map 49 Table 19 I2 C Interface Signal Location 50 Table 20 SPI Interface Signal Lo...

Page 8: ...tribution of the USB hub s U4 ports 90 Table 35 Universal USB pin header X33 signal description 90 Table 36 Display data connector signal description 94 Table 37 SPI and GPIO connector selection 95 Table 38 LVDS power connector X32 signal description 96 Table 39 Selection of the touch screen controller 97 Table 40 PHYTEC camera connector X5 100 Table 41 Selection of the audio codec 102 Table 42 I2...

Page 9: ... or low level signal while a 1 represents a logic one or high level signal Tables which describe jumper settings show the default position in bold blue text Text in blue italic indicates a hyperlink within or external to the document Click these links to quickly jump to the applicable URL part chapter table or figure References made to the phyCARD Connector always refer to the high density molex c...

Page 10: ...ss jumper these types of jumpers can be removed and placed by hand with no special tools PCB Printed circuit board POR Power on reset RTC Real time clock SMT Surface mount technology SBC Single Board Computer used in reference to the PCA A M1 phyCARD A M1 Single Board Computer VBAT SBC standby voltage input Table 1 Abbreviations and Acronyms used in this Manual Note The BSP delivered with the phyC...

Page 11: ...yCARD module lies in its layout and test PHYTEC s new phyCARD product family consists of a series of extremely compact embedded control engines featuring various processing performance classes while using the newly developed X Arc embedded bus standard The standardized connector footprint and pin assignment of the X Arc bus makes this new SBC generation extremely scalable and flexible This also al...

Page 12: ... ideas to market in the most timely and cost efficient manner For more information go to http www phytec com services Ordering Information The part numbering of the phyCARD has the following structure PCA A M1 xxxxxx Generation A First generation Performance class S small M middle L large XL largest Controller Number of specified performance class Assembly options depending on model In order to re...

Page 13: ...ly appropriately trained personnel such as electricians technicians and engineers handle and or operate these products Moreover PHYTEC products should not be operated without protection circuitry if connections to the product s pin header rows are longer than 3 m PHYTEC products fulfill the norms of the European Union s Directive for Electro Magnetic Conformity only in accordance to the descriptio...

Page 14: ...phyCARD M PCA A M1 xxx 6 PHYTEC Messtechnik GmbH 2010 L 750e_1 ...

Page 15: ...ctivity The X Arc bus exactly meets this requirement As well the location of the commonly used interfaces as the mechanical specifications are clearly defined All interface signals of PHYTEC s new X Arc bus are available on a single 100 pin high density pitch 0 635 mm connector allowing the phyCARDs to be plugged like a big chip into a target application The reduced complexity of the phyCARD SBC a...

Page 16: ...n the Freescale i MX35 No description of compatible microcontroller derivative functions is included as such functions are not relevant for the basic functioning of the phyCARD M The phyCARD M offers the following features Subminiature Single Board Computer 60 x 60 mm achieved through modern SMD technology Populated with the Freescale i MX35 microcontroller BGA400 packaging Improved interference s...

Page 17: ...ort Single supply voltage of 3 3V max 600mA with on board power management All controller required supplies generated on board 4 Channel LVDS 18Bit LCD Interface Support of standard 20 pin debug interface through JTAG connector One I2 C interfaces One SPI interfaces SD MMC card interface with DMA SSI Interface AC97 Optional LVDS Camera Interface1 3 GPIO IRQ ports 2 Power State outputs to support a...

Page 18: ...e USB OTG HS Phy I2 C3 D 24 BitLVDS Transmitter CS 10 Bit LVDS Deserializer SSI SPI 1 UART SDIO GPIO1_1 GPIO2_7 128MB to 1GB NAND Flash 8 bit EM USB Host Contr High Speed USB2 Host FS Phy RESET_IN_B POR_B GPIO GPIO3_0 GPIO GPIO2_29 30 IP Boot_Mode 0 1 10 100 Mbit Ethernet JTAG Debug Test Port Power VBat 3V3 3V3 Reset Input Reset I2 C Master USB Wake Up Card Edge C LVDS Display Interface LVDS Camer...

Page 19: ...Introduction 1 2 View of the phyCARD M Figure 2 Top view of the phyCARD M controller side PHYTEC Messtechnik GmbH 2010 L 750e_1 11 ...

Page 20: ...phyCARD M PCA A M1 xxx Figure 3 Bottom view of the phyCARD M connector side 12 PHYTEC Messtechnik GmbH 2010 L 750e_1 ...

Page 21: ... number of GND pins Corresponding GND X2 4A 8A 13A 4B 8B 13B Please refer to section 2 for information on additional GND Pins located at the phyCARD Connector X2 Caution We recommend connecting all available 3V3 input pins to the power supply system on a custom carrier board housing the phyCARD M and at least the matching number of GND pins neighboring the 3V3 pins In addition proper implementatio...

Page 22: ...numbering scheme for the phyCARD Connector is based on a two dimensional matrix in which column positions are identified by a letter and row position by a number Pin 1A for example is always located in the upper left hand corner of the matrix The pin numbering values increase moving down on the board Lettering of the pin connector rows progresses alphabetically from left to right refer to Figure 4...

Page 23: ...rdless of the fact that it could consist of more than one physical socketed connector The following figure illustrates the numbered matrix system It shows a phyCARD M with SMT phyCARD Connectors on its underside defined as dotted lines mounted on a Carrier Board In order to facilitate understanding of the pin assignment scheme the diagram presents a cross view of the phyCARD module showing these p...

Page 24: ... M It also provides the appropriate signal level interface voltages listed in the SL Signal Level column and the signal direction The Freescale i MX35 is a multi voltage operated microcontroller and as such special attention should be paid to the interface voltage levels to avoid unintentional damage to the microcontroller and other on board components Please refer to the Freescale i MX35 Referenc...

Page 25: ... In GND 25A 25B GND Bi USB_OTG_VBUS1 26A 26B nSuspend_to_RAM Out Bi USB_OTG_D1 27A 27B USB_D2 Bi Bi USB_OTG_D1 28A 28B USB_D2 Bi In USB_OTG_UID1 29A 29B nPower_off Out GND 30A 30B GND Bi SDIO_D0 31A 31B SDIO_D1 Bi Bi SDIO_D2 32A 32B SDIO_D3 Bi Out SDIO_CLK 33A 33B SDIO_CMD Bi GND 34A 34B GND Out SPI_CS0 35A 35B SPI_CS1 Out In SPI_RDY 36A 36B SPI_MOSI Out Out SPI_CLK 37A 37B SPI_MISO In GND 38A 38B...

Page 26: ... or 5V 7A X_MASTER_RESET I VDD_3V3 Active low Reset In 8A GND Ground 0V 9A X_TXOUT0 O LVDS LVDS Chanel 0 positive Output 10A X_TXOUT0 O LVDS LVDS Chanel 0 negative Output 11A X_TXOUT2 O LVDS LVDS Chanel 2 positive Output 12A X_TXOUT2 O LVDS LVDS Chanel 2 negative Output 13A GND Ground 0V 14A X_TXCLKOUT O LVDS LVDS Clock positive Output 15A X_TXCLKOUT O LVDS LVDS Clock negative output 16A X_CSI_MCL...

Page 27: ...34A GND Ground 0V 35A X_CSPI1_SS0 O VDD_3V3 SPI 1 Chip select 0 36A X_CSPI1_SPI_RDY O VDD_3V3 SPI 1 SPI data ready in Master mode 37A X_CSPI1_SCLK O VDD_3V3 SPI 1 clock 38A GND Ground 0V 39A X_UART1_TXD O VDD_3V3 Serial transmit signal UART 1 40A X_UART1_RTS O VDD_3V3 Request to send UART 1 41A GND Ground 0V 42A X_AC97_INT I O VDD_3V3 AC97 Interrupt Input 43A X_STXD4 O VDD_3V3 AC97 Transmit Output...

Page 28: ...ositive Input for Camera 15B X_RXIN O LVDS LVDS Receive negative Input for Camera 16B X_LOCK O VDD_3V3 Lock Output for Camera Interface 17B X_I2C3_SDA I O VDD_3V3 I2C Data 18B GND Ground 0V 19B X_ETH_LINK O VDD_3V3 Ethernet Speed Indicator Open Drain 20B X_ETH_RX I O ETH Receive positive input normal Transmit positive output reversed 21B X_ETH_RX I O ETH Receive negative input normal Transmit nega...

Page 29: ..._CSPI1_MISO I O VDD_3V3 SPI 1 Master data in slave data out 38B GND Ground 0V 39B X_UART1_RXD I VDD_3V3 Serial data receive signal UART 1 40B X_UART1_CTS I VDD_3V3 Clear to send UART 1 41B GND Ground 0V 42B X_SCK4 I VDD_3V3 AC97 Clock 43B X_STXFS4 O VDD_3V3 AC97 SYNC 44B X_AC97_nRESET O VDD_3V3 AC97 Reset 45B GND Ground 0V 46B X_SDIO_CD I VDD_3V3 SD MMC Card Detect for MMC SD SDIO 47B GPIO2_23 I O...

Page 30: ... positions and possible alternative positions and functions A detailed description of each solder jumper can be found in the applicable chapter listed in the table Note Jumpers not listed should not be changed as they are installed with regard to the configuration of the phyCARD M Figure 5 Typical jumper pad numbering scheme e g e g If manual jumper modification is required please ensure that the ...

Page 31: ...TYPE column to ensure you are using the correct type of jumper 0 Ohms 10k Ohms etc The jumpers are either 0805 package or 0402 package with a 1 8W or better power rating Figure 6 Jumper locations top view PHYTEC Messtechnik GmbH 2010 L 750e_1 23 ...

Page 32: ...phyCARD M PCA A M1 xxx Figure 7 Jumper locations bottom view 24 PHYTEC Messtechnik GmbH 2010 L 750e_1 ...

Page 33: ...ion It is not guaranteed that the standard serial memory populating the phyCARD M will have this write protection function Please refer to the corresponding memory data sheet for more detailed information 0R 0402 open EEPROM U6 is write protected closed EEPROM U6 is not write protected 7 3 2 J2 J2 selects if the fuse voltage VDD_FUSE is available only if the primary voltage VDD_3V3_IN is supplied ...

Page 34: ... fuses is required 7 3 2 J21 J21 selects rising or falling edge strobe for the LVDS Deserializer at U5 used for the display connectivity of the phyCARD M 10k 0805 1 2 rising edge strobe used for the LVDS camera signals 2 3 falling edge strobe used for the LVDS camera signals 13 1 J22 J22 selects rising or falling edge strobe for the LVDS Transmitter at U4 used for the display connectivity of the p...

Page 35: ... from the primary 3 3V supplied to the SBC For proper operation the phyCARD M must be supplied with a voltage source of 3 3V 5 with 600 mA load at the VCC pins on the phyCARD Connector X2 VDD_3V3_IN X2 1A 2A 3A 1B 2B 3B Connect all 3 3V VCC input pins to your power supply and at least the matching number of GND pins Corresponding GND X2 4A 8A 13A 4B 8B 13B Please refer to section 2 for information...

Page 36: ...ARD M provides an on board switching regulator U1 to source the five different voltages 1 375V 1 5V 1 8V 2 775V and 3 3V required by the processor and on board components Figure 8 presents a graphical depiction of the powering scheme The switching regulator has two input voltage rails as can be seen in Figure 8 3V3 and 3V3 Backup 3V3 is supplied only from the primary voltage input pins VDD_3V3_IN ...

Page 37: ...DRAM 2V775 internal I C Bus I2 C EEPROM 3V3 Backup PHYTEC Messtechnik GmbH 2010 L 750e_1 29 Figure 8 Power Supply Diagram 3V3 MC13892 DC DC Converter DC DC Converter LDO 1 5V 2 775V 1 8V 1 375V i MX35 Core On chip PLLs internal I C Bus I C EEPROM NVCC_EMI of the i MX35 DDR2 SDRAM supplied from VDD_3V3_IN and VBAT supplied from VDD_3V3_IN LDO ...

Page 38: ...etheless we recommend to supply external devices with the voltage VCC_Logic brought out at pins X2A5 and X2B5 of the phyCARD Connector and to use level shifters supplied with this voltage at one of the supply rails if you want to keep your application compatible to other phyCARDs with a different signal level This means that use of level shifters supplied with VCC_Logic allows converting the signa...

Page 39: ...ted to the PWRON2 input of the voltage regulator to allow implementing a power management by programming the power management IC The following table shows the location of the power management pins on the phyCARD Connector and the corresponding GPIOs of the i MX35 Pin Signal I O SL Description X2A4 8 X_WKUP I VDD_3V3 _BACKUP Wakeup Interrupt Input µC port GPIO3_0 at R4 and PMIC PWRON2 input X2B2 6 ...

Page 40: ...specification for the phyCARD family writing custom software to utilize pins nPower_off and nSuspend_to_RAM requires them to be configured as Open Collector Output Use of the power management features of the PMIC at U1 allows for a higher granularity in control of the power consumption To implement power management with the PMIC it can be programmed via an I2 C interface The MC13892 can be accesse...

Page 41: ...t available if VBAT is the only voltage source 2 3 Fuse voltage VDD_FUSE is also available when VBAT is the only voltage source J9 J9 selects if the 2 775V voltage rail is available only if the primary voltage VDD_3V3_IN is supplied or if it is also available when only VBAT is supplied 0R 0805 1 2 2 775V voltage rail is not available if VBAT is the only voltage source 2 3 2 775V voltage rail is al...

Page 42: ...on USB PHY configuration etc The i MX35 processor always begins fetching instruction from the internal bootstrap ROM sync flash or CS0 space The operational system boot mode of the i MX35 processor is determined by the configuration of the two external input pins BMOD 1 0 during the reset cycle The settings of these pins control where the system is boot from They are accessible via boot pins X_BOO...

Page 43: ...OD0 is the inverse of the input level of X_BOOT0 Because of pull up resistors located on the phyCARD M the default boot mode is External Boot which allows to boot from NAND Flash if the boot pins X_BOOT 1 0 are left open In other words to boot from NAND Flash no further settings at X_BOOT 1 0 are necessary To enter other boot modes a low level must be applied to X_BOOT 0 X2A50 and or X_BOOT 1 X2B5...

Page 44: ...ress cycles BT_MEM_CTRL other See i MX35 Reference Manual X_CSI_D12 BT_PAGE_SIZE 0 X_CSI_D13 BT_PAGE_SIZE 1 NAND Flash page size 00 512 bytes 01 2Kbytes 10 4Kbytes 11 Reserved X_CSI_D14 BT_ECC_SEL Defines 4 or 8 bit ECC 0 4 bit ECC 1 8 bit ECC X_CSI_D15 BT_USB_SRC 0 X_CSI_HSYNC BT_USB_SRC 1 USB PHY selection 00 UTMI PHY 01 ULPI PHY 10 Serial PHY ATLAS 11 Serial PHY ISP1301 X_CSI_VSYNC BT_BUS_WIDTH...

Page 45: ...echnik GmbH 2010 L 750e_1 37 The standard phyCARD M module with 128MB NAND Flash comes with a boot configuration of 0001010001 so the system will boot from the 8 bit NAND Flash at CS0 For further information please see the i MX35 Reference Manual ...

Page 46: ...nsity options Each RAM bank is comprised of two 16 bit wide DDR2 SDRAM chips configured for 32 bit access and operating at 133MHz In lower density configurations U9 and U11 populate the module and are accessed via SDRAM memory bank 0 using chip select signal CSD0 starting at 0x8000 0000 In higher density configurations U8 and U10 are also populated and are accessed via SDRAM memory bank 1 using ch...

Page 47: ...programming voltage is required As of the printing of this manual these NAND Flash devices generally have a life expectancy of at least 100 000 erase program cycles and a data retention rate of 10 years The NAND Flash memory is connected to the NAND Flash Controller NFC 7 3 I C EEPROM U6 The phyCARD M is populated with an ST 24W32C1 non volatile 4KByte EEPROM with an I C interface at U6 This memor...

Page 48: ... address bits A0 A1 and A2 The four upper address bits of the device are fixed at 1010 see ST 24W32C data sheet The remaining three lower address bits of the seven bit I C device address are configurable using jumpers J1 J3 and J4 J4 sets address bit A0 J1 address bit A1 and J3 address bit A2 Table 11 below shows the resulting seven bit I C device address for the eight possible jumper configuratio...

Page 49: ...isabling write access to the device The following configurations are possible EEPROM Write Protection State J16 Write access allowed closed Write protected open Table 12 EEPROM write protection states via J161 7 4 Memory Model There is no special address decoding device on the phyCARD M which means that the memory model is given according to the memory mapping of the i MX35 Please refer to the i M...

Page 50: ...r to the i MX35 Reference Manual for more information Due to compatibility reasons a card detect signal X_SDIO_CD is added to the SD MMC Card Interface This signal connects to port GPIO3_1 of the i MX35 Pin Signal I O SL Description X2A3 1 X_SD1_DAT A0 I O VDD_3V3 SD MMC Data line both in 1 bit and 4 bit mode X2A3 2 X_SD1_DAT A2 I O VDD_3V3 SD MMC Data line both in 1 bit and 4 bit mode X2A3 3 X_SD...

Page 51: ... not require any special precautions Nonetheless use of level shifters supplied with the voltage at pins X2A5 and X2B5 at one of the supply rails is necessary if you want to keep your application compatible to other phyCARDs with a different signal level Please refer to the chapter SD MMC in the phyCARD Design In Guide for more information about connecting an SD MMC Card slot to the phyCARD M ...

Page 52: ...peed USB HOST interface using the i MX35 s internal USB Host interface or optional high speed USB HOST interface derived from an external USB HOST controller at U16 4 Auto MDIX enabled 10 100 Ethernet PHY supporting the i MX35 Ethernet MAC 5 I2 C interface derived from third I2 C port of the i MX35 6 Serial Peripheral Interface SPI interface extended from the first SPI module of the i MX35 7 Synch...

Page 53: ...level of interface signals is different from the primary supply voltage on other phyCARDs Please pay special attention to the Signal Level SL column in the following tables Please refer to the phyCARD Design In Guide for more information about using the serial interfaces of the phyCARD M in customer applications 9 1 Universal Asynchronous Interface The phyCARD M provides a high speed universal asy...

Page 54: ...rd A for USB host USB Standard B for USB device or USB mini AB for USB OTG connector is all that is needed to interface the phyCARD M USB OTG functionality The applicable interface signals can be found on the phyCARD Connector as shown in Table 15 PIN SIGNAL I O SL DESCRIPTION X2A23 X_USBOTG_PW R O VDD_3V3 USB OTG Power switch output open drain X2A24 X_USBOTG_OC I VDD_3V3 USB OTG over current inpu...

Page 55: ...r at U16 They are installed prior to delivery and must not be changed An external USB Standard A for USB host connector is all that is needed to interface the phyCARD M USB Host functionality The applicable interface signals D D PSW FAULT can be found on the phyCARD Connector PIN SIGNAL I O SL DESCRIPTION X2B2 3 X_USB_PRW2 O VDD_3V3 USB HOST Power switch output open drain X2B2 4 X_USB_OC2 I VDD_3V...

Page 56: ...d Indicator Open Drain X2A2 0 X_ETH_TX O I V DD_3V3 Transmit positive output normal Receive positive input reversed X2A2 1 X_ETH_TX O I V DD_3V3 Transmit negative output normal Receive negative input reversed X2B1 9 X_ETH_LINK O V DD_3V3 Ethernet Speed Indicator Open Drain X2B2 0 X_ETH_RX I O V DD_3V3 Receive positive input normal Transmit positive output reversed X2B2 1 X_ETH_RX I O V DD_3V3 Rece...

Page 57: ...esistors on the analog signals ETH_RX ETH_TX are already populated on the module Connection to an external Ethernet magnetics should be done using very short signal traces The TPI TPI and TPO TPO signals should be routed as 100 Ohm differential pairs The same applies for the signal lines after the transformer circuit The carrier board layout should avoid any other signal lines crossing the Etherne...

Page 58: ... sticker attached to the module This number is a 12 digit HEX value 9 5 I2 C Interface The Inter Integrated Circuit I2 C interface is a two wire bidirectional serial bus that provides a simple and efficient method for data exchange among devices The i MX35 contains three identical and independent I2 C modules The interface of the third module is available on the phyCARD Connector whereas the first...

Page 59: ...N SIGNAL I O SL DESCRIPTION X2A3 5 X_CSPI1_SS0 O VDD_3V3 SPI 1 Chip select 0 X2B3 5 X_CSPI1_SS1 O VDD_3V3 SPI 1 Chip select 1 X2A3 6 X_CSPI1_SPI_R DY O VDD_3V3 SPI 1 SPI data ready in Master mode X2A3 7 X_CSPI1_SCLK O VDD_3V3 SPI 1 clock X2B3 6 X_CSPI1_MOSI I O VDD_3V3 SPI 1 Master data out slave data in X2B3 7 X_CSPI1_MISO I O VDD_3V3 SPI 1 Master data in slave data out Table 20 SPI Interface Sig...

Page 60: ...97_INT is used as input and output As output it signals which codec is supported by the phyCARD Use of this pin as an input enables to attach an external interrupt to port GPIO2_1 at W14 X_AC97_nRESET is connected to port GPIO3_2 at R5 of the i MX35 allowing to perform a software reset for the device attached to the interface Please also read the phyCARD Design In Guide for more information about ...

Page 61: ...vel is VDD_3V3 which is 3 3V and equals the supply voltage of the phyCARD M Thus connecting external devices to the phyCARD M does not require any special precautions This means that external devices could be supplied from the same power source as the phyCARD M Nonetheless we recommend to supply external devices with the voltage VCC_Logic brought out at pins X2A5 and X2B5 of the phyCARD Connector ...

Page 62: ...lash internal controller RAM or for debugging programs currently executing The JTAG interface extends to a 2 0 mm pitch pin header at X1 on the edge of the module PCB Figure 9 and show the position of the debug interface JTAG connector X1 on the phyCARD M module Figure 9 JTAG interface at X1 top view 54 PHYTEC Messtechnik GmbH 2010 L 750e_1 ...

Page 63: ...JTAG connector X1 only populates phyCARD M modules with order code PCA A M1 D JTAG connector X1 is not populated on phyCARD modules with order code PCA A M1 We recommend integration of a standard 2 mm pitch pin header connector in the user target circuitry to allow easy program updates via the JTAG interface See Table 23 for details on the JTAG signal pin assignment PHYTEC Messtechnik GmbH 2010 L ...

Page 64: ...n Table 23 JTAG connector X1 signal assignment Note Row A is on the controller side of the module and row B is on the connector side of the module PHYTEC offers a JTAG Emulator adapter order code JA 002 for connecting the phyCARD M to a standard emulator The JTAG Emulator adapter extends the signals of the module s JTAG connector to a standard ARM connector with 2 mm pin pitch The JA 002 therefore...

Page 65: ...w Pin Signal I O SL Description X2A9 X_TXOUT0 O LVDS LVDS Chanel 0 positive Output X2A10 X_TXOUT0 O LVDS LVDS Chanel 0 negative Output X2A11 X_TXOUT2 O LVDS LVDS Chanel 2 positive Output X2A12 X_TXOUT2 O LVDS LVDS Chanel 2 negative Output X2A14 X_TXCLKOU T O LVDS LVDS Clock positive Output X2A15 X_TXCLKOU T O LVDS LVDS Clock negative output X2B9 X_TXOUT1 O LVDS LVDS Chanel 0 positive Output X2B10 ...

Page 66: ... to the OpenLDI respectively Intel 24 0 standard Thus you can connect 18 bit as well as 24 bit LVDS displays to the phyCARD Table 25 and Table 26 show the recommended pixel mapping of the LVDS display For further information please see the phyCARD Design Guide Note Make sure that the LVDS display you want to use provides the same pin mapping as the phyCARD Normally this is only important for 24 bi...

Page 67: ...echnik GmbH 2010 L 750e_1 59 24 bit LVDS Display 1 2 3 4 5 6 7 CLK 1 1 0 0 0 1 1 A0 G2 R7 R6 R5 R4 R3 R2 A1 B3 B2 G7 G6 G5 G4 G3 A2 DE VSYNC HSYNC B7 B6 B5 B4 A3 0 B1 B0 G1 G0 R1 R0 Table 26 Pixel mapping of 24 bit LVDS display interface ...

Page 68: ...ation of the applicable interface signals X_CSI_MCLK X_LOCK X_RXIN X_RXIN on the phyCARD Connector Pin Signal I O SL Description X2A16 X_CSI_MCL K O VDD_3V3_I N Clock Output for Camera Interface X2B14 X_RXIN O LVDS LVDS Receive positive Input for Camera X2B15 X_RXIN O LVDS LVDS Receive negative Input for Camera X2B16 X_LOCK O VDD_3V3_I N Lock Output for Camera Interface Table 27 Camera Interface S...

Page 69: ...the PCB and approximately 3 1 mm on the top microcontroller side The board itself is approximately 1 4 mm thick Ref Des 9 17mm 10 44mm 7 17mm 56mm 31 11mm 0 635mm 8mm 4mm 4mm 7 24mm 4mm 10 45mm 9 2mm 60mm 6mm 4mm D2 7mm PhyCard S HOLE PAD D5 0mm Ref Des Figure 11 Physical dimensions Note To facilitate the integration of the phyCARD M into your design the footprint of the phyCARD M is available upo...

Page 70: ...erature 40 C to 125 C Operating temperature 0 C to 70 C commercial 20 C to 85 C industrial Humidity 95 r F not condensed Operating voltage VCC 3 3V Power consumption VCC 3 3 V 300mA typical Max 1 2 watts Conditions VCC 3 3 V VBAT 0 V 128MB DDR2 RAM 128MB NAND Flash Ethernet 400 MHz CPU frequency at 20 C These specifications describe the standard configuration of the phyCARD M as of the printing of...

Page 71: ...ween the two connected PCBs when the module is mounted on the corresponding carrier board In order to get the exact spacing the maximum component height 2 5 mm on the bottom side of the phyCARD must be subtracted Component height 6 mm Manufacturer Molex Number of pins per contact row 100 2 rows of 50 pins each Molex part number lead free 55091 1075 1074 header Component height 10 mm Manufacturer M...

Page 72: ...phyCARD M PCA A M1 xxx 15 Component Placement Diagram Figure 12 phyCARD M component placement top view 64 PHYTEC Messtechnik GmbH 2010 L 750e_1 ...

Page 73: ...Component Placement Diagram Figure 13 phyCARD M component placement bottom view PHYTEC Messtechnik GmbH 2010 L 750e_1 65 ...

Page 74: ...ly a hot air gun can be used to heat and loosen the bonds Caution If any modifications to the module are performed regardless of their nature the manufacturer guarantee is voided Integrating the phyCARD into a Target Application Successful integration in user target circuitry greatly depends on the adherence to the layout design rules for the GND connections of the phyCARD module For best results ...

Page 75: ...heral devices Support of different power modes of appropriate phyCARDs Full featured 4 line RS 232 transceiver supporting data rates of up to 120kbps hardware handshake and RS 232 connector Six USB Host interfaces USB OTG interface 10 100 Mbps Ethernet interface Complete Audio and Touchscreen interface LVDS display interface with separate connectors for data lines and display backlight supply volt...

Page 76: ...prototyping and software evaluation The Carrier Board is compatible with all phyCARDs This modular development platform concept is depicted in Figure 14 below and includes the following components the phyCARD M Module populated with the i MX35 processor and all applicable SBC circuitry such as DDR SDRAM Flash PHYs and transceivers to name a few the phyBASE which offers all essential components and...

Page 77: ...relevant to the operation of the phyCARD M mounted on the phyBASE Carrier Board Note Only features of the phyBASE which are supported by the phyCARD M are described Jumper settings and configurations which are not suitable for the phyCARD M are not described in the following chapters PHYTEC Messtechnik GmbH 2010 L 750e_1 69 ...

Page 78: ...ach peripheral for easy identification P1 9 4mm U4 U13 U6 U18 X32 U10 U1 U15 U26 U23 U3 XT1 U22 U12 U25 U19 BAT1 X34 U28 U2 U8 X4 U11 U20 U17 X27 U7 X9 U27 U29 U5 U21 U24 U14 U16 X8 U9 J1 X33 D38 X10 X28 X29 X30 X7 X5 X3 X2 X1 S2 S1 X26 S3 X6 IN OUT MIC AUDIO CAM RS232 USB Host USB OTG Ethernet PWR LVDS phyCARD Connector Expansion 1 Expansion 2 ON OFF Reset MMC SD card D29 D30 JP2 JP1 J2 J3 D26 D1...

Page 79: ...ata connector 17 3 7 1 X7 Dual USB Host connector 17 3 5 X8A Expansion connector 0 17 3 13 X9A Expansion connector 1 17 3 13 X10 Ethernet connector RJ45 with speed and link led 17 3 4 X26 Security Digital MultiMedia Card slot 17 3 14 X27 phyCARD Connector for mounting the phyCARD M 17 3 1 X28 Wall adapter input power jack to supply main board power 9 36 V 17 3 2 X29 USB On The Go connector 17 3 6 ...

Page 80: ...protected from overloading through connected peripherals 17 2 2Switches The phyBASE is populated with some switches which are essential for the operation of the phyCARD M module on the Carrier Board Figure 15 shows the location of the switches and push buttons Button Description See Section S1 System Reset Button system reset signal generation 17 3 16 S2 Power Button powering on and off main suppl...

Page 81: ...0 L 750e_1 73 Additionally a DIP Switch is available at S3 The following table gives an overview of the functions of the DIP switch Note The following table describes only settings suitable for the phyCARD M Other settings must not be used with the phyCARD M ...

Page 82: ...elected for audio dedicated touch contrl U28 for touch Analog Devices audio contrl U17 selected for audio dedicated touch contrl U28 for touch 17 3 9 S3_3 S3_4 0 0 Switches 3 and 4 of DIP Switch S3 configure the I2 C address for the communication between CPLD and phyCARD CPLD Address 0x80 S3_5 0 Switch 5 of DIP Switch S3 selects the interface used for the communication between CPLD and phyCARD I2C...

Page 83: ...nd the two GPIO_IRQ signals GIO0_IRQ GPIO1_IRQ to two of the three available connectors SS0 GPIO0 expansion 0 X8A SS1 GPIO1 expansion 1 X9A SS0 GPIO0 expansion 0 X8A SS1 GPIO1 display data connector X6 SS0 GPIO0 expansion 1 X9A SS1 GPIO1 display data connector X6 17 3 7 1 17 3 11 17 3 12 17 3 13 Table 30 phyBASE DIP Switch S3 descriptions1 1 Default settings are in bold blue text ...

Page 84: ...B4 amber led D20 yellow USB5 amber led D21 yellow USB6 amber led D22 yellow USB7 amber led D23 green USB1 green led D24 green USB2 green led D25 green USB3 green led D26 green USB4 green led D27 green USB5 green led D28 green USB6 green led D29 green USB7 green led D30 red USB HUB global led 17 3 5 D37 green 5V supply voltage for peripherals on the phyBASE D38 green supply voltage of the phyCARD D...

Page 85: ...The phyCARD M on the phyBASE PHYTEC Messtechnik GmbH 2010 L 750e_1 77 Note Detailed descriptions of the assembled connectors jumpers and switches can be found in the following chapters ...

Page 86: ...at pin 1 is always marked by a square footprint in the jumper location diagrams that follow Figure 17 provides a detailed view of the phyBase jumpers and their default settings Before making connections to peripheral connectors it is advisable to consult the applicable section in this manual for setting the associated jumpers e g JP1 e g e g J1 Figure 16 Typical jumper numbering scheme Table 32 pr...

Page 87: ...N OUT MIC AUDIO CAM RS232 USB Host USB OTG Ethernet PWR LVDS phyCARD Connector Expansion 1 Expansion 2 ON OFF Reset MMC SD card D29 D30 JP2 JP1 J2 J3 D26 D16 D23 D17 D24 D18 D25 D19 D20 D27 D21 D28 D22 D39 D40 D37 D41 X7 X29 J1 Figure 17 phyBASE jumper locations The following conventions were used in the Jumper column of the jumper table Table 32 J solder jumper JP removable jumper PHYTEC Messtech...

Page 88: ...klight VCC12V Backlight disabled JP2 closed VCC12V Backlight connected to power supply only 12V DC power supplies allowed 17 3 7 2 1 2 Jumper J1 selects the function of the AC97 interrupt Pendown signal of the Audio Touch controller at U1 is connected to AC97 interrupt J1 2 3 GPIO2_IRQ output of the Audio Touch controller at U1 connected to AC97 interrupt 17 3 7 3 J2 closed Jumper J2 configures th...

Page 89: ...ice address of LED dimmer set to 0xC2 1 2 Jumper J3 configures the I2 C address of the touch screen controller at U28 I2 C device address set to 0x88 J3 2 3 I2 C device address set to 0x82 17 3 7 3 17 3 10 Table 32 phyBASE jumper descriptions8 8 Default settings are in bold blue text ...

Page 90: ...4 U14 U16 X8 U9 J1 D38 X10 X30 X5 X3 X2 X1 S2 S1 X26 S3 X6 IN OUT MIC AUDIO CAM RS232 USB Host USB OTG Ethernet PWR LVDS phyCARD Connector Expansion 1 Expansion 2 ON OFF Reset MMC SD card D29 D30 JP2 JP1 J2 J3 D26 D16 D23 D17 D24 D18 D25 D19 D20 D27 D21 D28 D22 D40 D37 D41 X7 X29 X28 A B 1 50 D39 P1 Figure 18 phyCARD M SBC Connectivity to the Carrier Board Connector X27 on the Carrier Board provid...

Page 91: ...1 X7 X29 X28 Figure 19 Power adapter Caution Do not use a laboratory adapter to supply power to the Carrier Board Power spikes during power on could destroy the phyCARD module mounted on the Carrier Board Do not change modules or jumper settings while the Carrier Board is supplied with power Permissible input voltage at X28 9 36 V DC unregulated The required current load capacity of the power supp...

Page 92: ...9 green VCC3V3 led D40 green VCC3V3STBY led D41 green VSTBY led Table 33 LEDs assembled on the Carrier Board Note For powering up the phyCARD the following actions have to be done 1 Plug in the power supply connector All power LEDs should light up and the phyCARD puts serial output to serial line 0 at P1 2 For powering down the phyCARD M button S2 should be pressed for a minimum time of 2000ms 3 P...

Page 93: ...wer switch In SUSPEND mode only the standby voltage VSTBY for the phyCARD M and the standby voltage VCC3V3STBY of the phyBASE itself are generated This means the phyCARD M is supplied only by VSTBY The RUN and OFF state can be entered using the power button S2 as described in the gray box above It is also possible to enter OFF state with the help of the phyCARD s nPower_off signal GPIO2_30 at T5 o...

Page 94: ... Expansion 2 ON OFF Reset MMC SD card D29 D30 JP2 JP1 J2 J3 D26 D16 D23 D17 D24 D18 D25 D19 D20 D27 D21 D28 D22 D40 D37 D41 X7 X29 D39 Figure 21 UART1 connection interface at connector P1 Connector P1 is a DB9 sub connector and provides a connection interface to UART1 of the i MX35 The TTL level signals from the phyCARD M are converted to RS 232 level signals UART1 provides only two handshake sign...

Page 95: ...mbH 2010 L 750e_1 87 1 2 3 4 7 6 5 8 9 Pin 2 TxD RS232 Pin 7 RTS RS232 Pin 3 RxD RS232 Pin 8 CTS RS232 Pin 5 GND Figure 22 UART1 connector P1 signal description The RS 232 interface is hard wired and no jumpers must be configured for proper operation ...

Page 96: ...ARD Connector Expansion 1 Expansion 2 ON OFF Reset MMC SD card D29 D30 JP2 JP1 J2 J3 D26 D16 D23 D17 D24 D18 D25 D19 D20 D27 D21 D28 D22 D40 D37 D41 X7 X29 X10 D39 P1 Figure 23 Ethernet interface at connector X10 The Ethernet interface of the phyCARD is accessible at an RJ45 connector X10 on the Carrier Board Due to its characteristics this interface is hard wired and can not be configured via jum...

Page 97: ... interface of the phyCARD is accessible via the USB hub controller U4 on the Carrier Board The controller supports control of input USB devices such keyboard mouse or USB key The USB hub has 7 downstream facing ports Three ports extend to standard USB connectors at X7 dual USB A and X30 USB A A fourth port connects to 9 pin header row X33 These interfaces are compliant with USB revision 2 0 The re...

Page 98: ...USB1 X30 USB A USB2 X6 40 pin FCC pins 16 and 17 USB3 X8 20 pin header row pins 19 and 20 USB4 X9 20 pin header row pins 19 and 20 USB5 X33 9 pin header row see table below USB6 X7A bottom USB A USB7 X7B top USB A Table 34 Distribution of the USB hub s U4 ports Pin number Signal name Description 1 USB5_VBUS USB5 Power Supply 3 USB5_D USB5 Data 5 USB5_D USB5 Data 7 GND Ground 2 4 6 8 10 NC Not conn...

Page 99: ...9 D30 JP2 JP1 J2 J3 D26 D16 D23 D17 D24 D18 D25 D19 D20 D27 D21 D28 D22 D40 D37 D41 X7 X29 D39 Figure 25 USB OTG interface at connector X29 The USB OTG interface of the phyCARD is accessible at connector X29 USB Mini AB on the Carrier Board This interface is compliant with USB revision 2 0 No jumper settings are necessary for using the USB OTG port The phyCARD supports the On The Go feature The Un...

Page 100: ...large number of different displays varying in resolution signal level type of the backlight Pin out etc In order not to limit the range of displays connectable to the phyCARD the phyBASE has no special display connector suitable only for a small number of displays The new concept intends the use of an adapter board e g phyBASE LCD interface LCD 014 to attach a special display or display family to ...

Page 101: ...rrupt input 6 VCC3V3 Power supply display 7 I2C_SCL I2C Clock Signal 8 I2C_SDA I2C Data Signal 9 GND Ground 10 LS_BRIGHT PWM brightness Output 11 VCC3V3 Power Supply Display 12 PWR_KEY Power on off Button 13 DISP_ENA Display enable signal 14 PHYWIRE Hardware Introspection Interface for internal use only 15 GND Ground 16 USB2_D USB2 data 9 17 USB2_D USB2 data 1 18 GND Ground 19 TXOUT0 LVDS data cha...

Page 102: ...KOUT LVDS clock channel positive output 33 GND Ground 34 TP_X Touch 35 TP_X Touch 36 TP_Y Touch 37 TP_Y Touch 38 TP_WP Touch 39 GND Ground 40 LS_ANA Light sensor Analog Input Table 36 Display data connector signal description The X Arc bus signals for the SPI interface and the display interrupt input are shared with the corresponding signals on the expansion connectors X8A and X9A Because of that ...

Page 103: ...ector X6 SS0 GPIO01 expansion 1 X9A SS1 GPIO11 display data connector X6 Table 37 SPI and GPIO connector selection The default setting does not connect the SPI interface and the GPIO of the X Arc bus to the display data connector The Light sensor Analog Input at pin 40 extends to an A D converter which is connected to the I2 C bus at address 0xC8 write and 0XC9 read 10 GPIO0 GPIO1_1 at L16 and GPI...

Page 104: ...isplay 7 GND Ground 8 VCC5V 5V power supply display 9 GND Ground 10 LS_BRIGHT PWM brightness output 11 VCC12V_BL 12V Backlight power supply 12 VCC12V_BL 12V Backlight power supply Table 38 LVDS power connector X32 signal description The PWM signal at pin 10 can be used to control the brightness of a display s backlight It is generated by an LED dimmer The LED dimmer is connected to the I2 C bus at...

Page 105: ...M9712L audio touch codec at U1 allows connecting 4 and 5 wire touch panels whereas the STMPE811 touch panel controller at U28 is suitable for 4 wire touch panels only Switches 1 and 2 of DIP Switch S3 select which controller is used to process the touch panel signals The different configurations are shown in Table 39 Button Setting Description S3_1 S3_2 0 0 0 1 1 0 Switches 1 and 2 of DIP Switch S...

Page 106: ...ult configuration selects the pendown signal to be attached to pin X2A42 of the phyCARD Connector If the dedicated touch screen controller at U28 is chosen the touch screen data is available at the I2 C interface of the X Arc bus The controller s slave address can be selected with jumper J3 refer to section 17 2 4 The default address of the controller is 0x88 write and 0x89 read The interrupt outp...

Page 107: ...USB Host USB OTG Ethernet PWR LVDS phyCARD Connector Expansion 1 Expansion 2 ON OFF Reset MMC SD card D29 D30 JP2 JP1 J2 J3 D26 D16 D23 D17 D24 D18 D25 D19 D20 D27 D21 D28 D22 D40 D37 D41 X7 X29 X28 D39 Figure 27 Camera interface at connectors X5 The phyCARD M has an optional camera interface This interface extends from the phyCARD Connector to the RJ45 socket X5 on the Carrier Board The table bel...

Page 108: ...k GmbH 2010 L 750e_1 Pin Signal Name Description 1 RXIN LVDS Input 2 RXIN LVDS Input 3 RX_CLK LVDS Clock 4 I2C_SDA I2C Data 5 I2C_SCL I2C Clock 6 RXCLK LVDS Clock 7 VCC_CAM Power supply camera 3 3V 8 GND Ground Table 40 PHYTEC camera connector X5 ...

Page 109: ... phyCARD Connector Expansion 1 Expansion 2 ON OFF Reset MMC SD card D29 D30 JP2 JP1 J2 J3 D26 D16 D23 D17 D24 D18 D25 D19 D20 D27 D21 D28 D22 D40 D37 D41 X7 X29 X28 D39 Figure 28 Audio interface at connectors X1 X2 X3 The AC97 HDA interface on the phyCARD connects to a Wolfson WM9712L U1 or AD1986A U17 audio codec controller on the Carrier Board Switches 1 and 2 of DIP Switch S3 select which codec...

Page 110: ...Line_OUTL Line_OUTR Audio Inputs X1 Microphone Inputs MIC1 MIC2 X3 Line Input Line_INL Line_INR Please refer to the audio codec s reference manual for additional information regarding the special interface specification 17 3 10 I2 C Connectivity The I2 C interface of the X Arc bus is available at different connectors on the phyBASE The following table provides a list of the connectors and pins wit...

Page 111: ...Some of the addresses can be configured by jumper Table 43 lists the addresses already in use The table shows only the default address Please refer to section 17 2 4 for alternative address settings Device Address used write read Jumper LED dimmer U21 0xC0 0xC1 J2 RTC U3 0xA2 0xA3 A D converter U22 0xC8 0xC9 Touch screen controller U28 0x88 0x89 J3 CPLD U25 0x80 0x81 S3_3 S3_4 Table 43 I2 C addres...

Page 112: ...ing Description S3_7 S3_8 0 0 0 1 1 x SS0 GPIO012 expansion 0 X8A SS1 GPIO11 expansion 1 X9A SS0 GPIO01 expansion 0 X8A SS1 GPIO11 display data connector X6 SS0 GPIO01 expansion 1 X9A SS1 GPIO11 display data connector X6 Table 44 SPI connector selection 17 3 12 User programmable GPIOs Two GPIO0_IRQ and GPIO1_IRQ of the three GPIO Interrupt signals available at the X Arc bus are freely available Th...

Page 113: ... X8A X9A The expansion connectors X8A and X9A provide an easy way to add other functions and features to the phyBASE Standard interfaces such as USB SPI and I2 C as well as different supply voltages and one GPIO are available at the pin header rows As can be seen in Figure 29 the location of the connectors allows to expand the functionality without expanding the physical dimensions Mounting wholes...

Page 114: ...8 0 0 0 1 1 x SS0 GPIO013 expansion 0 X8A SS1 GPIO11 expansion 1 X9A SS0 GPIO01 expansion 0 X8A SS1 GPIO11 display data connector X6 SS0 GPIO01 expansion 1 X9A SS1 GPIO11 display data connector X6 Table 45 SPI and GPIO connector selection 13 GPIO0 GPIO1_1 at L16 and GPIO1 GPIO2_23 at V3 of the i MX35 ...

Page 115: ..._SS_SLOT1 X8A SPI chip select expansion port 0 X9A SPI chip select expansion port 1 12 SPI1_MOSI SPI master output slave input 13 SPI1_SCLK SPI clock output 14 SPI1_MISO SPI master input slave output 15 SPI1_RDY SPI data ready input master mode only 16 SLOT0_IRQ SLOT1_IRQ X8A Interrupt input expansion port 0 X9A Interrupt input expansion port 1 17 GND Ground 18 GND Ground 19 USB3_D USB4_D X8A USB3...

Page 116: ...SD card D29 D30 JP2 JP1 J2 J3 D26 D16 D23 D17 D24 D18 D25 D19 D20 D27 D21 D28 D22 D40 D37 D41 X7 X29 D39 Figure 30 SD Card interface at connector X26 The phyCARD Carrier Board provides a standard SDHC card slot at X26 for connection to SD MMC interface cards It allows easy and convenient connection to peripheral devices like SD and MMC cards Power to the SD interface is supplied by sticking the ap...

Page 117: ...JP2 JP1 J2 J3 D26 D16 D23 D17 D24 D18 D25 D19 D20 D27 D21 D28 D22 D40 D37 D41 X7 X29 X28 D39 Figure 31 Boot Mode Selection Jumper JP1 The boot mode jumper JP1 is provided to configure the boot mode of the phyCARD M after a reset By default the boot mode jumper is open configuring the phyCARD M for booting from the Flash device Closing jumper JP1 results in start of the on chip boot strap software ...

Page 118: ..._1 Jumper Setting Description open Jumper JP1 selects the boot device of the phyCARD M FLASH enabled as Boot device14 1 2 Serial Bootloader1 3 4 Internal Bootloader1 JP1 1 2 3 4 Startup Mode1 14 please see section 6 for more information on the different boot modes ...

Page 119: ... USB Host USB OTG Ethernet PWR LVDS phyCARD Connector Expansion 1 Expansion 2 ON OFF Reset MMC SD card D29 D30 JP2 JP1 J2 J3 D26 D16 D23 D17 D24 D18 D25 D19 D20 D27 D21 D28 D22 D40 D37 D41 X7 X29 X28 D39 Figure 32 System Reset Button S1 The phyCARD Carrier Board is equipped with a system reset button at S1 Pressing the button will not only reset the phyCARD mounted on the phyBASE but also the peri...

Page 120: ...25 D19 D20 D27 D21 D28 D22 D40 D37 D41 X7 X29 X28 D39 For real time or time driven applications the phyBASE is equipped with an RTC 8564 Real Time Clock at U3 This RTC device provides the following features Serial input output bus I2 C address 0xA2 write 0xA3 read Power consumption Bus active 400 kHz 1 mA Bus inactive CLKOUT inactive 275 nA Clock function with four year calendar Century bit for ye...

Page 121: ...the RTC interrupt is to be used as software interrupt via a corresponding interrupt input of the processor Note After connection of the supply voltage the Real Time Clock generates no interrupt The RTC must be first initialized see RTC Data Sheet for more information Use of a coin cell at BAT1 allows to buffer the RTC 17 3 18 PLD at U25 The phyBASE is equipped with a Lattice LC4256V PLD at U25 Thi...

Page 122: ...10 X28 X29 X30 X7 P1 X5 X3 X2 X1 S2 S1 X26 S3 X6 IN OUT MIC AUDIO CAM RS232 USB Host USB OTG Ethernet PWR LVDS phyCARD Connector Expansion 1 Expansion 2 ON OFF Reset MMC SD card D29 D30 JP2 JP1 J2 J3 D26 D16 D23 D17 D24 D18 D25 D19 D20 D27 D21 D28 D22 D40 D37 D41 D39 Figure 33 Carrier Board Physical Dimensions Please contact us if a more detailed dimensioned drawing is needed to integrate the phyB...

Page 123: ...on History Date Version numbers Changes in this manual 01 07 2009 Manual L 750e_0 First draft Preliminary documentation Describes the phyCARD M with phyBASE Baseboard 10 06 2010 Manual L 750e_1 Final version matching phyCARD M s PCB No 1328 1 and 1333 1 for the phyBASE ...

Page 124: ...mensions 62 Display Interface 57 E EEPROM 38 39 EEPROM Write Protection 41 EMC 5 Emulator 56 F Fast Ethernet Controller 48 Features 8 67 FEC 48 G General Purpose I Os 53 GND Connection 66 H Humidity 62 I I C EEPROM 39 I2 C Interface 50 I2 C Memory 25 I2 C2 Bus 25 IC Identification Module 26 J J1 25 40 J13 26 J16 25 41 J2 25 32 33 J21 26 60 J22 26 58 J3 25 40 J4 25 40 J9 25 32 33 JA 002 56 JTAG Int...

Page 125: ...agement 31 Power Supply 13 Programming Voltage 26 R RS 232 Level 46 RTC 112 RTC Interrupt 113 S SD MMC Card Interfaces 42 SDRAM 38 Serial Interfaces 44 SMT Connector 14 SPEED LED 88 SPI Interface 51 SSI Interface 51 Standby Voltage 28 Storage Temperature 62 Supply Voltage 27 System Configuration 34 System Memory 38 System Power 27 T Technical Specifications 61 U U10 38 U11 38 U13 39 U16 47 U4 26 5...

Page 126: ...phyCARD M PCA A M1 xxx 118 PHYTEC Messtechnik GmbH 2010 L 750e_1 W Weight 62 WM9712L 97 98 101 X X1 54 X29 91 ...

Page 127: ...t phyCARD M Document number L 750e_1 June 2010 How would you improve this manual Did you find any mistakes in this manual page Submitted by Customer number Name Company Address Return to PHYTEC Technologie Holding AG Postfach 100403 D 55135 Mainz Germany Fax 49 6131 9221 33 ...

Page 128: ...Published by PHYTEC Messtechnik GmbH 2010 Ordering No L 750e_1 Printed in Germany ...

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