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PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
15. IEEE 1149.1 Compatible JTAG Controller
An IEEE 1149.1 compatible Test Access Port (TAP) controller and associated TAP pins are provided to support boundary
scan in PI7C7100 for board-level continuity test and diagnostics. The TAP pins assigned are TCK, TDI, TDO, TMS and
TRST#. All digital input, output, input/output pins are tested except TAP pins and clock pin.
The IEEE 1149.1 Test Logic consists of a TAP controller, an instruction register, and a group of test data registers including
Bypass, Device Identification and Boundary Scan registers. The TAP controller is a synchronous 16 state machine driven
by the Test Clock (TCK) and the Test Mode Select (TMS) pins. An independent power on reset circuit is provided to ensure
the machine is in TEST_LOGIC_RESET state at power-up. The JTAG signal lines are not active when the PCI resource
is operating PCI bus cycles.
PI7C7100 implements 3 basic instructions: BYPASS, SAMPLE/PRELOAD, EXTEST.
15.1 Boundary Scan Architecture
Boundary-scan test logic consists of a boundary-scan register and support logic. These are accessed through a Test
Access Port (TAP). The TAP provides a simple serial interface that allows all processor signal pins to be driven and/or
sampled, thereby providing direct control and monitoring of processor pins at the system level.
This mode of operation is valuable for design debugging and fault diagnosis since it permits examination of connections
not normally accessible to the test system. The following subsections describe the boundary-scan test logic elements:
TAP pins, instruction register, test data registers and TAP controller. Figure 15-1 illustrates how these pieces fit together
to form the JTAG unit.
15.1.1 TAP Pins
The PI7C7100’s TAP pins form a serial port composed of four input connections (TMS, TCK, TRST# and TDI) and one output
connection (TDO). These pins are described in Table 15-1. The TAP pins provide access to the instruction register and
the test data registers.
15.1.2 Instruction Register
The Instruction Register (IR) holds instruction codes. These codes are shifted in through the Test Data Input (TDI) pin. The
instruction codes are used to select the specific test operation to be performed and the test data register to be accessed.
The instruction register is a parallel-loadable, master/slave-configured 2-bit wide, serial-shift register with latched outputs.
Data is shifted into and out of the IR serially through the TDI pin clocked by the rising edge of TCK. The shifted-in instruction
becomes active upon latching from the master stage to the slave stage. At that time the IR outputs along with the TAP
finite state machine outputs are decoded to select and control the test data register selected by that instruction. Upon
latching, all actions caused by any previous instructions terminate.
Boundary-Scan Register
Control and Clock Signals
TAP
Controller
Instruction
Register
Bypass Register
TDO
TDI
TMS
TCK
TRST#
TAP Pins
PI7C7100 System Pins
Figure 15-1. Test Access Port Block Diagram
