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Appendix B
PI7C7100
3-Port PCI Bridge
B-5
04/18/00
ADVANCE INFORMATION
Frequently Asked Questions
1.
What is the function of SCAN_EN?
SCAN_EN is for a full scan test or S_CLKIN select. During SCAN mode, SCAN_EN will be driven to logic “0”
or “logic “1” depending on functionality. During normal mode, if SCAN_EN is connected to logic “0” (JP7 in
the 1-2 position), S_CLKIN will be used for PLL test only when PL_TM is active. If SCAN_EN is connected to
logic “1” (JP7 in the 2-3 position), S_CLKIN will be the clock input for the secondary buses. All secondary
clock outputs, S_CLKOUT [15:0], are still derived from P_CLK with 0-10ns delay. The S_CLKOUT [15:0]
should be disabled by programming the bits [15:0] in both configuration registers 1 and 2 at offset 68h.
2.
What is the function of SCAN_TM#?
SCAN_TM# is for full scan test and power on reset for the PLL. SCAN_TM# should be connected to logic “1” or
to an RC path (R1 and C13) during normal operation.
3.
How do you use the external arbiter?
a)
Disable the on chip arbiter by connecting S_CFN to logic “1” (JP4 in the 2-3 position).
b)
Use S1_REQ0# as GRANT and S1_GNT0# as REQUEST on the S1 bus.
c)
Use S2_REQ0# as GRANT and S2_GNT0# as REQUEST on the S2 bus.
4.
What is the purpose of having JP1, JP2, and JP3?
JP1, JP2, and JP3 are designed for easy access to the primary bus signals. You may connect any of these pins
to an oscilloscope or a logic analyzer for observation. No connection is required for normal operation. The
following table indicates which bus signals correspond to which pins.
5.
What is the purpose for having U17, U19, and U20?
U17, U19, and U20 are designed for easy access to the digital ground planes for observation.
6.
How is the evaluation board constructed?
The evaluation board is a six-layer PCB. The top and bottom layers (1 and 6) are for signals, power, and ground
routing. Layer 2 and layer 5 are ground planes. Layer 3 is a digital 3.3V power plane. Layer 4 is a digital 5V
power plane with an island of analog 3.3V power.
7.
What is the function of S_CLKIN?
The S_CLKIN pin is a test pin for the on chip PLL when PLL_TM is set to logic “1”. During normal operation, if
PLL_TM is set to logic “0”, SCAN_TM# is set to logic “1”, and SCAN_EN is set to logic “1”, then S_CLKIN will
be the clock input for both the secondary buses. However, the S_CLKOUT [15:0] are still derived by program-
ming bits [15:0] in both configuration registers 1 and 2 at offset 68h.
8.
What clock frequency combinations does the PI7C7100 support?
Primary Bus
Secondary (1 and 2) Buses
33MHz
33MHz
9.
How are the JTAG signals being connected?
The JTAG signals consist of TRST#, TCK, TMS, TDI, and TDO. All the mentioned signals have weak internal
pull-up connections. Therefore, no connection is needed if you want the JTAG circuit to be disabled. If you want
to activate the JTAG circuit, you need to connect all five signals according to the JTAG specification (IEEE
1149).
1
2
3
4
5
6
7
8
9
0
1
1
1
2
1
3
1
4
1
5
1
6
1
2
P
J
Q
E
R
9
2
D
A
6
2
D
A
3
E
B
C
1
2
D
A
8
1
D
A
2
E
B
C
Y
D
R
I
K
C
O
L
R
A
P
4
1
D
A
1
1
D
A
0
E
B
C
6
D
A
5
D
A
0
D
A
3
P
J
1
3
D
A
8
2
D
A
5
2
D
A
3
2
D
A
0
2
D
A
7
1
D
A
E
M
A
R
F
L
E
S
V
D
R
R
E
P
1
E
B
C
3
1
D
A
0
1
D
A
8
D
A
4
D
A
2
D
A
D
N
G
1
P
J
T
N
G
0
3
D
A
7
2
D
A
4
2
D
A
2
2
D
A
9
1
D
A
6
1
D
A
Y
D
R
I
P
O
T
S
R
R
E
S
5
1
D
A
2
1
D
A
9
D
A
7
D
A
3
D
A
1
D
A
