Pericom PI7C7100 Manual Download Page 33 | Manualshive

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09/18/00 Rev 1.1

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PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

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Table 4-8. Responses to Posted Write Target Termination

Note that when a target retry or target disconnect is returned and posted write data associated with that transaction
remains in the write buffers, PI7C7100 initiates another write transaction to attempt to deliver the rest of the write data.
If there is a target retry, the exact same address will be driven as for the initial write transaction attempt. If a target
disconnect is received, the address that is driven on a subsequent write transaction attempt will be updated to reflect
the address of the current DWORD. If the initial write transaction is Memory-Write-and-Invalidate transaction, and a
partial delivery of write data to the target is performed before a target disconnect is received, PI7C7100 will use the
memory write command to deliver the rest of the write data. It is because an incomplete cache line will be transferred
in the subsequent write transaction attempt.

After the PI7C7100 makes 2

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(default) write transaction attempts and fails to deliver all posted write data associated with

that transaction, PI7C7100 asserts P_SERR# if the primary SERR# enable bit is set (bit 8 of command register for
secondary bus S1 or S2) and posted-write-non-delivery bit is not set. The posted-write-non-delivery bit is the bit 2 of
P_SERR# event disable register (offset 64h). PI7C7100 will report system error. See Section 7.4 for a discussion of system
error conditions.

4.8.3.3 Delayed Read Target Termination Response

When PI7C7100 initiates a delayed read transaction, the abnormal target responses can be passed back to the initiator.
Other target responses depend on how much data the initiator requests. Table 4–9 shows the response to each type
of target termination that occurs during a delayed read transaction.

PI7C7100 repeats a delayed read transaction until one of the following conditions is met:

• PI7C7100 completes at least one data transfer.
• PI7C7100 receives a master abort.
• PI7C7100 receives a target abort.
• PI7C7100 makes 2

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(default) read attempts resulting in a response of target retry.

Table 4-9. Responses to Delayed Read Target Termination

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Summary of Contents for PI7C7100

Page 1: ...ring Drive San Jose California 95131 Telephone 1 877 PERICOM 1 877 737 4266 Fax 408 435 1100 E mail nolimits pericom com Internet http www pericom com 2000 Pericom Semiconductor Corporation Pericom Semiconductor Corporation Rev 1 1 查询PI7C7100供应商捷多邦专业PCB打样工厂 24小时加急出货 ...

Page 2: ...he labeling can be reasonably expected to result in a significant injury to the user 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness Pericom Semiconductor Corporation reserves the right to make changes to its products or s...

Page 3: ...4 4 5 1 Posted Write Transactions 14 4 5 2 Memory Write and Invalidate Transactions 15 4 5 3 Delayed Write Transactions 15 4 5 4 Write Transaction Address Boundaries 16 4 5 5 Buffering Multiple Write Transactions 16 4 5 6 Fast Back to Back Write Transactions 16 4 6 Read Transactions 17 4 6 1 Prefetchable Read Transactions 17 4 6 2 Non prefetchable Read Transactions 17 4 6 3 Read Pre fetch Address ...

Page 4: ...ringGuidelines 32 6 3 OrderingRules 33 6 4 Data Synchronization 34 7 ErrorHandling 35 7 1 Address Parity Errors 35 7 2 DataParityErrors 35 7 2 1 Configuration Write Transactions to Configuration Space 35 7 2 2 Read Transactions 36 7 2 3 Delayed Write Transactions 36 7 2 4 Posted Write Transactions 38 7 3 DataParityErrorReportingSummary 39 7 4 SystemError SERR Reporting 45 8 ExclusiveAccess 46 8 1 ...

Page 5: ...1 13 2 22 Config Register 1 or 2 Memory Base Register read write bit 15 0 offset 20h 62 13 2 23 ConfigRegister1or2 MemoryLimitRegister read write bit31 16 offset20h 62 13 2 24 Config Register 1 or 2 Prefetchable Memory Base Register read write bit 15 0 offset 24h 62 13 2 25 ConfigRegister1or2 PrefetchableMemoryLimitRegister read write bit31 16 offset24h 62 13 2 26 Config Register 1 or 2 I O Base A...

Page 6: ... 13 2 54 Config Register 1 Primary Successful Memory Read Count Register read write bit 31 0 offset 98h 69 13 2 55 Config Register 1 Primary Successful Memory Write Count Register read write bit 31 0 offset 9Ch 69 14 BridgeBehavior 70 14 1 Bridge Actions for Various Cycle Types 70 14 2 Transaction Ordering 70 14 3 Abnormal Termination Initiated by Bridge Master 71 14 3 1 Master Abort 71 14 3 2 Par...

Page 7: ...Conditions 80 17 1 256 PinPBGAPackageDrawing 81 List of Tables 4 1 PCI Transaction 13 4 2 Write Transaction Forwarding 14 4 3 Write Transaction Disconnect Address Boundaries 16 4 4 Read Pre fetch Address Boundaries 17 4 5 Read Transaction Pre fetching 18 4 6 Device Number to IDSEL S1_AD or S2_AD Pin Mapping 21 4 7 Delayed Write Target Termination Response 24 4 8 Responses to Posted Write Target Te...

Page 8: ...15 Downstream Posted Memory Write Transaction P 33MHz S 33MHz A 9 16 Downstream Posted Memory Write Transaction S2 33MHz S1 33MHz A 10 17 Downstream Posted Memory Write Transaction S1 33MHz S2 33MHz A 10 18 Upstream Posted Memory Write Transaction S 33MHz P 33MHz A 11 19 Downstream Flow Through Posted Memory Write Transaction P 33MHz S 33MHz A 11 20 Downstream Flow Through Posted Memory Write Tran...

Page 9: ...r delay transactions Three 128 byte FIFOs for posted memory transactions Enhancedaddressdecoding 32 bit I O address range 32 bit memory mapped I O address range VGA addressing and VGA palette snooping ISA aware mode for legacy support in the first 64KB of I O address range InterruptHandling PCI interrupts are routed through an external interrupt concentrator Supports system transaction ordering ru...

Page 10: ...INFORMATION Figure 1 2 PI7C7100 in Redundant Application Figure 1 1 PI7C7100 on the System Board S1 PCI Bus S2 PCI Bus PI7C7100 CPU NB Slot Slot System Memory PCI Device PCI Device PI7C7100 System Primary PCI Bus PI7C7100 S1 PCI Bus Master Controller Redundant Controller S2 PCI Bus System Primary PCI Bus S1 S1 S2 S2 Figure 1 3 PI7C7100 on Network Switching Hub CPU PCI Bus 32 33 PI7C7100 PCI Bus 32...

Page 11: ...1234567890123456789012123456789012345678901234567890121234567 PI7C7100 3 Port PCI Bridge ADVANCE INFORMATION Configuration Register 1 Arbiter Arbiter Secondary Interface B Secondary Interface A Secondary PCI Bus A Transaction Queue 1 Transaction Queue 2 Transaction Queue 3 Configuration Register 2 Primary PCI Bus Secondary PCI Bus B Primary Interface 2 PI7C7100 Block Diagram Figure 2 1 PI7C7100 Bl...

Page 12: ...P e l d i s u b g n i r u D d e t r e s s a e r a Y D R T _ P d e t r e s s a s i T N G _ P n e h w l e v e l c i g o l 0 3 E B C _ P 9 1 V 6 1 U 2 1 U 9 V B P s e l b a n E e t y B d n a m m o C y r a m i r P e t y b d n a d l e i f d n a m m o c d e x e l p i t l u M e p y t n o i t c a s n a r t e h t s e v i r d r o t a i t i n i e h t e s a h p s s e r d d a g n i r u D d l e i f e l b a n e ...

Page 13: ... C 7 I P o t s s e c c a n o i t a r u g i f n o c 0 e p y T r o f e n i l t c e l e s p i h c s a d e s U e c a p s n o i t a r u g i f n o c R R E P _ P 5 1 Y S T S P r o r r E y t i r a P y r a m i r P W O L e v i t c A r o f d e t c e t e d s i r o r r e y t i r a p a t a d a n e h w d e t r e s s A e d a o t n e v i r d s i t i d e t a t s 3 g n i e b e r o f e B e c a f r e t n i y r a m i r...

Page 14: ... p a t a d e t i r w r o F y t i r a p s s e r d d a s i Y D R I _ 2 S r o Y D R I _ 1 S r e t f a k c o l c e n o d i l a v s i d n a t u p n i t u p t u o n a s i R A P _ 2 S r o R A P _ 1 S e s a h p a t a d d a e r r o F d e t r e s s a d e t r e s s a s i Y D R T _ 2 S r o Y D R T _ 1 S r e t f a k c o l c e n o d i l a v s i d n a D A _ 1 S e h t r e t f a e l c y c e n o d e t a t s 3 s i R...

Page 15: ...s i s e r a h g u o r h t p u d e l l u p y l l a n r e t x e 0 7 T N G _ 1 S 0 7 T N G _ 2 S 2 1 B 1 1 C 4 1 A 3 1 B 6 1 B 4 1 D 8 1 B 6 1 D 1 R 4 P 1 U 4 L 3 M 4 N 2 K 1 L O P W O L e v i t c A t n a r G y r a d n o c e S e h t s s e c c a o t n i p s i h t s t r e s s a 0 0 1 7 C 7 I P s e l c y c k c o l c I C P 2 t s a e l t a r o f n i p s i h t s t r e s s a e d 0 0 1 7 C 7 I P s u b y r a ...

Page 16: ... S 7 T N G _ 2 S y l e v i t c e p s e r N E _ N A C S 5 U U I C l o r t n o C e l b a n E n a c s l l u F n o i t a r e p o t f i h s n i s i n a c s l l u f W O L s i N E _ N A C S n e h W n o i t a r e p o l e l l a r a p n i s i n a c s l l u f H G I H s i N E _ N A C S n e h W e v i t c a s i M T _ N A C S f i f I e d o m l a m r o n n i W O L d e i t e b d l u o h s N E _ N A C S e v i t c a...

Page 17: ... S V 6 A 0 1 D A _ 2 S B P 7 A 0 E B C _ 2 S B P 8 A S S V 9 A 2 D A _ 2 S B P 0 1 A S S V 1 1 A 7 T U O K L C _ S S T P 2 1 A 6 Q E R _ 1 S U I P 3 1 A 5 T U O K L C _ S S T P 4 1 A 6 T N G _ 1 S O P 5 1 A S S V 6 1 A 2 Q E R _ 1 S U I P 7 1 A S S V 8 1 A 1 T U O K L C _ S S T P 9 1 A 0 T U O K L C _ S S T P 0 2 A S S V 1 B 6 1 D A _ 2 S B P 2 B Y D R I _ 2 S S T S P 3 B K C O L _ 2 S S T S P 4 B...

Page 18: ...S O P 7 1 D 4 2 D A _ 1 S B P 8 1 D S S V 9 1 D 5 2 D A _ 1 S B P 0 2 D 6 2 D A _ 1 S B P 1 E 0 2 D A _ 2 S B P 2 E D D V 3 E S S V 4 E 9 1 D A _ 2 S B P 7 1 E 1 2 D A _ 1 S B P 8 1 E 2 2 D A _ 1 S B P 9 1 E 3 2 D A _ 1 S B P 0 2 E 3 E B C _ 1 S B P 1 F 3 E B C _ 2 S B P 2 F 3 2 D A _ 2 S B P 3 F 2 2 D A _ 2 S B P 4 F 1 2 D A _ 2 S B P 7 1 F 8 1 D A _ 1 S B P 8 1 F D D V 9 1 F 9 1 D A _ 1 S B P 0 ...

Page 19: ... G _ 2 S O P 4 M 1 1 T U O K L C _ S S T P 7 1 M 0 1 D A _ 1 S B P 8 1 M S S V 9 1 M 1 1 D A _ 1 S B P 0 2 M 2 1 D A _ 1 S B P 1 N S S V 2 N D D V 3 N 2 1 T U O K L C _ S S T P 4 N 4 T N G _ 2 S O P 7 1 N 6 D A _ 1 S B P 8 1 N 7 D A _ 1 S B P 9 1 N 8 D A _ 1 S B P 0 2 N 9 D A _ 1 S B P 1 P 4 Q E R _ 2 S U I P 2 P 5 Q E R _ 2 S U I P 3 P 3 1 T U O K L C _ S S T P 4 P 6 T N G _ 2 S O P 7 1 P 5 D A _...

Page 20: ... P B P 3 1 V Y D R I _ P B P 4 1 V K C O L _ P S T S P 5 1 V D D V 6 1 V 5 1 D A _ P B P 7 1 V S S V 8 1 V N E 6 6 M _ P 9 1 V 0 E B C _ P B P 0 2 V 3 D A _ P B P 1 W S M T U I C 2 W I D T U I C 3 W N E _ 1 S U I P 4 W N E _ 2 S U I P 5 W H S U L F _ P I P 6 W Q E R _ P S T P 7 W 0 3 D A _ P B P 8 W 8 2 D A _ P B P 9 W 4 2 D A _ P B P 0 1 W 3 2 D A _ P B P 1 1 W S S V 2 1 W 7 1 D A _ P B P 3 1 W E...

Page 21: ...Y Y Y 1 1 0 0 e t i r w O I Y Y Y Y 0 0 1 0 d e v r e s e R N N N N 1 0 1 0 d e v r e s e R N N N N 0 1 1 0 d a e r y r o m e M Y Y Y Y 1 1 1 0 e t i r w y r o m e M Y Y Y Y 0 0 0 1 d e v r e s e R N N N N 1 0 0 1 d e v r e s e R N N N N 0 1 0 1 d a e r n o i t a r u g i f n o C N Y Y N 1 1 0 1 e t i r w n o i t a r u g i f n o C y l n o 1 e p y T Y Y Y y l n o 1 e p y T Y 0 0 1 1 e l p i t l u m ...

Page 22: ...esdisconnectboundaries seeSection4 5 4forwriteaddressboundariesandSection4 6 3readaddress boundaries 4 5 Write Transactions Write transactions are treated as either posted write or delayed write transactions Table 4 2 shows the method of forwarding used for each type of write operation n o i t c a s n a r T f o e p y T g n i d r a w r o F f o e p y T e t i r w y r o m e M y r o m e m A G V t p e c...

Page 23: ...tions ThePI7C7100disconnectsMemoryWriteandInvalidatecommandsatalignedcachelineboundaries Thecachelinesize value in the cache line size register gives the number of DWORD in a cache line If the value in the cache line size register does meet the memory write and invalidate conditions the PI7C7100 returns a target disconnect to the initiator either on a cache line boundary or when the posted write b...

Page 24: ...ted and delayed write transactions are ordered 4 5 6 Fast Back to Back Write Transactions PI7C7100 can recognize and post fast back to back write transactions When PI7C7100 cannot accept the second transaction because of buffer space limitations it returns a target retry to the initiator claimstheaccessbyassertingDEVSEL andreturnsTRDY totheinitiator toindicatethatthewritedatawastransferred If the ...

Page 25: ...memory read transactions that fall into non prefetchable memory space If extra read transactions could have side effects for example when accessing a FIFO use non prefetchable read transactions to those locations Accordingly if it is important to retain the value of the byte enable bits during the data phase usenon prefetchablereadtransactions Iftheselocationsaremappedinmemoryspace usethememoryrea...

Page 26: ...transfer has been completed PI7C7100 does not initiate any further attempts to read more data IfPI7C7100isunabletoobtainreaddatafromthetargetafter224 default or232 maximum attempts PI7C7100willreport systemerror Thenumberofattemptsisprogrammable PI7C7100alsoassertsP_SERR iftheprimarySERR enable bit is set in the command register See Section 7 4 for information on the assertion of P_SERR Once PI7C7...

Page 27: ...guration commands All registers are accessible in configuration space only In addition to accepting configuration transactions for initialization of its own configuration space the PI7C7100 also forwards configuration transactions for device initialization in hierarchical PCI systems as well as for special cycle generation To support hierarchical PCI bus systems two types of configuration transact...

Page 28: ...ormat so that the secondary bus device can respond to it Type 1 to Type 0 translations are performed only in the downstream direction that is PI7C7100 generates a Type 0 transaction only on the secondary bus and never on the primary bus PI7C7100 responds to a Type 1 configuration transaction and translates it into a Type 0 transaction on the secondary bus when the following conditions are met duri...

Page 29: ...anslated to a Type 0 configuration command or to a special cycle transaction by a downstream PCI to PCI bridge Downstream Type 1 to Type 1 forwarding occurs when the following conditions are met during the address phase The lowest two address bits are equal to 01b The bus number falls in the range defined by the lower limit exclusive in the secondary bus number register and the upper limit inclusi...

Page 30: ...dress bits AD 7 2 is equal to 000000b The bus number is equal to the value in the secondary bus number register in configuration space for downstream forwarding or equal to the value in the primary bus number register in configuration space for upstream forwarding The bus command on CBE is a configuration write command When PI7C7100 initiates the transaction on the target interface the bus command...

Page 31: ...If PI7C7100 is delivering posted write data when it terminates the transaction because the master latency timer expires it initiates another transaction to deliver the remaining write data The address of the transaction is updated to reflect the address of the current DWORD to be delivered If PI7C7100 is pre fetching read data when it terminates the transaction because the master latency timer exp...

Page 32: ...n o C r o t a i t i n i o t y r t e r t e g r a t g n i n r u t e R t c e n n o c s i d t e g r a T s e s a h p a t a d e l p i t l u m f i y l n o r e f s n a r t a t a d t s r i f h t i w r o t a i t i n i o t t c e n n o c s i d g n i n r u t e R d e t s e u q e r t r o b a t e g r a T e c a f r e t n i t e g r a t n i t i b t r o b a t e g r a t d e v i e c e r t e S r o t a i t i n i o t t r ...

Page 33: ...ransaction attempt AfterthePI7C7100makes224 default writetransactionattemptsandfailstodeliverallpostedwritedataassociatedwith that transaction PI7C7100 asserts P_SERR if the primary SERR enable bit is set bit 8 of command register for secondary bus S1 or S2 and posted write non delivery bit is not set The posted write non delivery bit is the bit 2 of P_SERR eventdisableregister offset64h PI7C7100w...

Page 34: ...The delayed transaction queue is full and the transaction cannot be queued A transaction with the same address and command has been queued A locked sequence is being propagated across PI7C7100 and the write transaction is not a locked transaction The target bus is locked and the write transaction is a locked transaction Use more than 16 clocks to accept this transaction For delayed read transactio...

Page 35: ...4 3 Target Abort PI7C7100 returns a target abort to an initiator when one of the following conditions is met PI7C7100 is returning a target abort from the intended target When PI7C7100 returns a target abort to the initiator it sets the signaled target abort bit in the status register corresponding to the initiator interface 4 9 Concurrent Mode Operation The Bridge can be configured to run in conc...

Page 36: ...wnstream in S1 bus and not in the marked address range for downstream in S2 bus the transaction will be forwarded to S1 bus instead of primary bus 5 2 I O Address Decoding PI7C7100 uses the following mechanisms that are defined in the configuration space to specify the I O address space for downstream and upstream forwarding I O base and limit address registers The ISA enable bit The VGA mode bit ...

Page 37: ...eset to 0000 0FFFh Note The initial states of the I O base and I O limit address registers define an I O range of 0000 0000h to 0000 0FFFh whichisthebottom4KBofI Ospace WritetheseregisterswiththeirappropriatevaluesbeforesettingeithertheI Oenable bit or the master enable bit in the command register in configuration space 5 2 2 ISA Mode PI7C7100supportsISAmodebyprovidinganISAenablebitinthebridgecont...

Page 38: ...tmemory mappedI Obaseaddressregisteratconfiguration offset20handbya16 bitmemory mappedI Olimitaddressregisteratoffset22h Thetop12bitsofeachoftheseregisters correspond to bits 31 20 of the memory address The low 4 bits are hardwired to 0 The lowest 20 bits of the memory mappedI Obaseaddressareassumedtobe00000h whichresultsinanaturalalignmenttoa1MBboundary Thelowest 20 bits of the memory mapped I O ...

Page 39: ...both be set to the same value while the lower base register is set greater than the lower limit register Otherwise the upper 32 bit base must be greater than the upper 32 bit limit 5 4 VGA Support PI7C7100 provides two modes for VGA support VGA mode supporting VGA compatible addressing VGA snoop mode supporting VGA palette forwarding 5 4 1 VGA Mode When a VGA compatible device exists downstream fr...

Page 40: ...are terminated by target retry on the initiator bus and are queued in the delayed transaction queue Delayed read completion transactions comprised of all memory read I O read configuration read transactions Delayed read completion transactions complete on the target bus and the read data is queued in the read data buffers A delayed read completion transaction proceeds in the direction opposite tha...

Page 41: ...ly queued posted write transaction must push the posted write data ahead of it The posted write transaction must complete on the target bus before the delayed read request can be attempted on the target bus The read transaction can be to the same location as the write data so if the read transaction were to pass the write transaction it would return stale data 3 A delayed read completion must pull...

Page 42: ...on queue 6 4 Data Synchronization Data synchronization refers to the relationship between interrupt signaling and data delivery The PCI Local Bus Specification Revision 2 1 provides the following alternative methods for synchronizing data and interrupts The device signaling the interrupt performs a read of the data just written software The device driver performs a read operation to any register i...

Page 43: ... system error bit in the status register if both the following conditions are met The SERR enable bit is set in the command register The parity error response bit is set in the command register When PI7C7100 detects an address parity error on the secondary interface the following events occur If the parity error response bit is set in the bridge control register PI7C7100 does not claim the transac...

Page 44: ...hed and is not read by the initiator on the secondary bus the data is discarded and the data with bad parity is not returned to the initiator PI7C7100 completes the transaction normally PI7C7100 returns to the initiator the data and parity that was received from the target When the initiator detects a parity error on this read data and is enabled to report it the initiator asserts PERR two cycles ...

Page 45: ...that is at the head of the posted data queue Note that the parity bit is not compared when determining whether the transaction matches those in the delayed transaction queues Two cases must be considered When parity error is detected on the initiator bus on a subsequent re attempt of the transaction and was not detected on the target bus When parity error is forwarded back from the target bus Ford...

Page 46: ...ndary interface PI7C7100 captures and forwards the bad parity condition to the primary bus PI7C7100 completes the transaction normally During downstream write transactions when a data parity error is reported on the target secondary bus by the target s assertion of S_PERR the following events occur PI7C7100 sets the data parity detected bit in the status register of secondary interface if the pari...

Page 47: ... e t i r w d e t s o P m a e r t s p U y r a d n o c e S x x 1 e t i r w d e y a l e D m a e r t s n w o D y r a m i r P x x 0 e t i r w d e y a l e D m a e r t s n w o D y r a d n o c e S x x 0 e t i r w d e y a l e D m a e r t s p U y r a m i r P x x 0 e t i r w d e y a l e D m a e r t s p U y r a d n o c e S x x 1 x don t care Table 7 1 shows setting the detected parity error bit in the status ...

Page 48: ...y r a d n o c e S x x 0 e t i r w d e y a l e D m a e r t s n w o D y r a m i r P x x 0 e t i r w d e y a l e D m a e r t s n w o D y r a d n o c e S x x 1 e t i r w d e y a l e D m a e r t s p U y r a m i r P x 1 0 e t i r w d e y a l e D m a e r t s p U y r a d n o c e S x x Table 7 3 Setting Primary Interface Data Parity Detected Bit d e t c e t e d y r a d n o c e S t i b r o r r e y t i r a p...

Page 49: ... r w d e t s o P m a e r t s n w o D y r a m i r P x x 1 e t i r w d e t s o P m a e r t s n w o D y r a d n o c e S 1 x 0 e t i r w d e t s o P m a e r t s p U y r a m i r P x x 0 e t i r w d e t s o P m a e r t s p U y r a d n o c e S x x 0 e t i r w d e y a l e D m a e r t s n w o D y r a m i r P x x 1 e t i r w d e y a l e D m a e r t s n w o D y r a d n o c e S 1 x 0 e t i r w d e y a l e D m...

Page 50: ...x 1 1 e t i r w d e t s o P m a e r t s n w o D y r a d n o c e S x x 1 e t i r w d e t s o P m a e r t s p U y r a m i r P x x 1 e t i r w d e t s o P m a e r t s p U y r a d n o c e S x x 0 e t i r w d e y a l e D m a e r t s n w o D y r a m i r P x 1 02 e t i r w d e y a l e D m a e r t s n w o D y r a d n o c e S 1 1 1 e t i r w d e y a l e D m a e r t s p U y r a m i r P x x 1 e t i r w d e y...

Page 51: ... i r P x x 1 e t i r w d e t s o P m a e r t s n w o D y r a d n o c e S x x 1 e t i r w d e t s o P m a e r t s p U y r a m i r P x x 0 e t i r w d e t s o P m a e r t s p U y r a d n o c e S 1 x 1 e t i r w d e y a l e D m a e r t s n w o D y r a m i r P x x 1 e t i r w d e y a l e D m a e r t s n w o D y r a d n o c e S x x 02 e t i r w d e y a l e D m a e r t s p U y r a m i r P 1 1 0 e t i r ...

Page 52: ... r T e p y T n o i t c e r i D s a w r o r r e e r e h w s u B d e t c e t e d y r a d n o c e S y r a m i r P s t i b e s n o p s e r r o r r e y t i r a p d e t r e s s a e d 1 d a e R m a e r t s n w o D y r a m i r P x x 1 1 d a e R m a e r t s n w o D y r a d n o c e S x x 1 d a e R m a e r t s p U y r a m i r P x x 1 d a e R m a e r t s p U y r a d n o c e S x x 1 e t i r w d e t s o P m a e...

Page 53: ...he SERR forward enable bit is set in the bridge control register In addition PI7C7100 also sets the received system error bit in the secondary status register PI7C7100 also conditionally asserts P_SERR for any of the following reasons Target abort detected during posted write transaction Master abort detected during posted write transaction Posted write data discarded after 224 default attempts to...

Page 54: ... retry is signaled to the initiator the initiator must relinquish the lock on the primary bus and therefore the lock is not yet established Thefirstlockedtransactionmustbeareadtransaction Subsequentlockedtransactionscanbereadorwritetransactions Posted memory write transactions that are a part of the locked transaction sequence are still posted Memory read transactions that are a part of the locked...

Page 55: ...e last locked transaction is a delayed transaction PI7C7100 has already completed the transaction on the secondary bus In this example as soon as PI7C7100 detects that the initiator has relinquished the LOCK signal by sampling it in the de asserted state while FRAME is de asserted PI7C7100 de asserts the LOCK signal on the target busassoonaspossible Becauseofthisbehavior LOCK maynotbede assertedun...

Page 56: ...d at PI7C7100 and PI7C7100 has a transaction to initiate on the primary bus PI7C7100 starts the transaction if P_GNT was asserted during the previous cycle 9 2 Secondary PCI Bus Arbitration PI7C7100 implements an internal secondary PCI bus arbiter This arbiter supports two sets of eight external masters in additiontoPI7C7100 Theinternalarbitercanbedisabled andanexternalarbitercanbeusedinsteadforse...

Page 57: ...is busy that is either S1_FRAME S2_FRAME or S1_IRDY S2_IRDY is asserted the arbiter can de assert one grant and assert another grant during the same PCI clock cycle 9 2 2SecondaryBusArbitrationUsinganExternalArbiter The internal arbiter is disabled when the secondary bus central function control pin S_CFN is tied high An external arbiter must then be used When S_CFN is tied high PI7C7100 reconfigu...

Page 58: ...maryinterfaceissynchronizedtotheprimaryclock input P_CLK and the secondary interface is synchronized to the secondary clock The secondary clock is derived internally from the primary clock P_CLK through an internal PLL PI7C7100 operates at a maximum frequency of 33 MHz 10 2 Secondary Clock Outputs PI7C7100 has 16 secondary clock outputs S_CLKOUT 15 0 that can be used as clock inputs for up to sixt...

Page 59: ...ce signals associated with the Secondary S1 or S2 port The S1_RESET or S2_RESET in asserting and de asserting edges can be asynchronous to P_CLK The chip reset bit in the diagnostic control register is set Signal S1_RESET or S2_RESET remains asserted until a configuration write operation clears the secondary reset bit and the secondary clock serial mask has been shifted in WhenS1_RESET orS2_RESET ...

Page 60: ...y r o m e m h g u o r h t s s a p n i h t i w s i s s e r d d a f I 2 h g u o r h t s s a p d n a m i a l c r e t s i g e r l a n r e t n i e g d i r b d e p p a m y r o m e m o t s t n i o p s s e r d d a f I 3 h g u o r h t s s a p t o n o d r e t s i g e r o t s s e c c a t i m r e p d n a s s e c c a l a n r e t n i r o f m i a l c t o n o d d n a h g u o r h t s s a p t o n o d e s i w r e h ...

Page 61: ...e g r a t e h t f I 2 h g u o r h t s s a p d n a m i a l c s u b y r a d n o c e s e h t o t l a u q e t o n t u b e t i r w n o i t a r u g i f n o c 1 e p y t a s a d e g n a h c n u e r o n g i e s i w r e h t O 3 t s e u q e r e l c y c l a i c e p s s a e t i r w n o i t a r u g i f n o C I I I h 7 n o i t c n u f h F 1 e c i v e d s s a p d n a m i a l c s u b y r a d n o c e s s e g d i r ...

Page 62: ...i c e p s t o n e t i r w n o i t a r u g i f n o c 1 e p y T I I e r o n g I t s e u q e r e l c y c l a i c e p s s a e t i r w n o i t a r u g i f n o C I I I h 7 n o i t c n u f h F 1 e c i v e d h g u o r h t s s a p d n a m i a l c s u b y r a m i r p s e g d i r b e h t s i s u b t e g r a t e h t f I 1 e l c y c l a i c e p s a s a s e s u b f o e g n a r n i t i s i r o n s u b y r a m i ...

Page 63: ... a m i r P r e b m u N h 8 1 s u t a t S y r a d n o c e S t i m i L O I e s a B O I h C 1 t i m i L y r o m e M e s a B y r o m e M h 0 2 t i m i L y r o m e M e l b a h c t e f e r P e s a B y r o m e M e l b a h c t e f e r P h 4 2 d e v r e s e R h C 2 h 8 2 s t i B 6 1 r e p p U t i m i L O I s t i B 6 1 r e p p U e s a B O I h 0 3 D I m e t s y s b u S D I r o d n e V m e t s y s b u S h 4 3...

Page 64: ... i B 6 1 r e p p U t i m i L O I s t i B 6 1 r e p p U e s a B O I h 0 3 D I m e t s y s b u S D I r o d n e V m e t s y s b u S h 4 3 d e v r e s e R h 8 3 l o r t n o C e g d i r B n i P t p u r r e t n I d e v r e s e R h C 3 l o r t n o C r e t i b r A l o r t n o C c i t s o n g a i D l o r t n o C p i h C h 0 4 t i m i L y r o m e M e l b a h c t e f e r P y r a m i r P e s a B y r o m e M e...

Page 65: ... i r a p l a m r o n 1 0 o t t e s e R 5 e l b a n E p o o n S e t t e l a P A G V W R s e s s e c c a e t t e l a p e l b i t a p m o c A G V o t e s n o p s e r s e g d i r b s l o r t n o C e c a f r e t n i y r a m i r p e h t n o s e s s e c c a e t t e l a p A G V e r o n g i 0 e c a f r e t n i y r a m i r p e h t n o s e t i r w e t t e l a p A G V o t e s n o p s e r e l b a n e 1 h 8 C 3...

Page 66: ... d i l a v n I d n a e t i r W y r o m e M 0 o t t e s e R 3 e l c y C l a i c e p S e l b a n E O R n o i t a t n e m e l p m i e l c y c l a i c e p s o N 0 o t t e s e R 2 r e t s a M s u B e l b a n E W R e c a f r e t n i y r a m i r p e h t n o r e t s a m a s a e t a r e p o o t y t i l i b a s e g d i r b s l o r t n o C e l b a s i d d n a e c a f r e t n i y r a m i r p e h t n o n o i t...

Page 67: ... r e t s a M h t i w 0 o t t e s e R 8 2 t r o b A t e g r a T d e v i e c e R C W R d e t a n i m r e t e r a s n o i t c a s n a r t n e h w e c i v e d r e t s a m a y b 1 o t t e S t r o b A t e g r a T h t i w 0 o t t e s e R 7 2 t r o b A t e g r a T d e l a n g i S C W R t r o b A t e g r a T a r e v e n e h w e c i v e d t e g r a t a y b t e s e b d l u o h S s r u c c o e l c y c 0 o t t...

Page 68: ... register is implemented but not being used internally Reset to 00h 13 2 16 Config Register 1 or 2 Secondary Bus Number Register read write bit 15 8 offset 18h Programmed with the number of the PCI bridge secondary bus interface This value is set by software during configu ration Reset to 00h 13 2 17 Config Register 1 or 2 Subordinate Bus Number Register read write bit 23 16 offset 18h Programmed ...

Page 69: ...8 2 t r o b A t e g r a T d e v i e c e R C W R h t i w d e t a n i m r e t e r a s n o i t c a s n a r t n e h w e c i v e d r e t s a m a y b 1 o t t e S t r o b A t e g r a T 0 o t t e s e R 7 2 t r o b A t e g r a T d e l a n g i S C W R s r u c c o e l c y c t r o b A t e g r a T a r e v e n e h w e c i v e d t e g r a t a y b t e s e b d l u o h S t e s e r r e t f a 0 e b d l u o h S 0 o t ...

Page 70: ...upper twelve bits are reset to 000h The lower four bits are read only and are set to 0 The lower 20 address bits 19 0 are as sumed to be 00000h 13 2 25 Config Register 1 or 2 Prefetchable Memory Limit Register read write bit 31 16 offset 24h This register defines the upper limit address of the memory mapped address range for forwarding the cycle through the bridge The upper twelve bits correspond ...

Page 71: ...a n E A G V W R s e s s e r d d a e l b i t a p m o c A G V o t e s n o p s e r s e g d i r b e h t s l o r t n o C s e s s e r d d a O I d n a y r o m e m e l b i t a p m o c A G V d r a w r o f t o n o d 0 y r a d n o c e s o t y r a m i r p m o r f y r a d n o c e s o t y r a m i r p m o r f s s e r d d a O I d n a y r o m e m e l b i t a p m o c A G V d r a w r o f 1 s g n i t t e s r e h t o ...

Page 72: ... d i r b y H W R 2 d n a 1 s u b y r a d n o c e s m o r f s r e t s a m r o f n o i t a r t i b r a d e x i M 0 7 Q E R _ 2 S d n a 0 7 Q E R _ 1 S r o f n o i t a r t i b r a e t a r a p e s 0 n o i t a r t i b r a r o f 0 3 Q E R _ 2 S h t i w d e x i m e r a 0 3 Q E R _ 1 S 1 d e s u s i r e t i b r a e n o y l n O 0 o t t e s e R 6 2 d e v r e s e R W R 0 o t t e s e R 5 2 f o y t i r o i r P...

Page 73: ...s t p m e t t a t e s s i r e t s i g e r d n a m m o c e h t n i t i b e l b a n e R R E S d n a 0 s i t i b s i h t n e h w s r u c c o 0 o t t e s e R 5 e t i r w d e y a l e D r e v i l e d n o n W R r e f s n a r t o t e l b a n u s i t i n e h w R R E S _ P t r e s s a o t 0 0 1 7 C 7 I P f o y t i l i b a s l o r t n o C 2 r e t f a a t a d e t i r w d e y a l e d 4 2 s r u c c o t n e v e ...

Page 74: ...s i D 0 k c o l C d e l b a n e s i 0 T U O K L C _ S 0 s i t i b r e h t i e f I d e l b a s i d s i 0 T U O K L C _ S 1 e r a s t i b h t o b n e h W t i B n o i t c n u F e p y T n o i t p i r c s e D 4 1 5 1 e l b a s i D 7 k c o l C W R d e l b a n e s i 5 1 T U O K L C _ S 0 s i t i b r e h t i e f I d e l b a s i d s i 5 1 T U O K L C _ S 1 e r a s t i b h t o b n e h W 2 1 3 1 e l b a s i ...

Page 75: ...o i t a r u g i f n o c e h t n i D I m e t s y s b u S d n a t c e t o r p e t i r W 0 e l b a n e e t i r W 1 0 o t t e s e R 4 W M E M y r a d n o c e S e l b a n E s a i l A d n a m m o C W R d e t s o p n o n g n i h c t a m r o f m s i n a h c e m n o i t c e t e d s e g d i r b e h t s l o r t n o C e c a f r e t n i y r a d n o c e s n o r o t a i t i n i m o r f e l c y c y r t e r e t i ...

Page 76: ... e t i r W 0 e l b a n e e t i r W 1 0 o t t e s e R 4 W M E M y r a d n o c e S d n a m m o C e l b a n E s a i l A W R d e t s o p n o n g n i h c t a m r o f m s i n a h c e m n o i t c e t e d s e g d i r b e h t s l o r t n o C e c a f r e t n i y r a d n o c e s n o r o t a i t i n i m o r f e l c y c y r t e r e t i r w y r o m e m t c a x e e b o t s a h d n a m m o C 0 I W M E M o t t n e...

Page 77: ...ad write bit 31 0 offset 84h This register stores the successful I O write count on the secondary interface which will be updated when the sam pling timer is active Reset to 0000_0000h 13 2 50 Config Register 1 or 2 Successful Memory Read Count Register read write bit 31 0 offset 88h This register stores the successful memory read count on the secondary interface which will be updated when the sam...

Page 78: ... M y r a m i r P n o t e g r a T g n i d o c e d y b n o i t a u t i s s i h t s t c e t e d t I d n o p s e r t o n s e o d 0 0 1 7 C 7 I P t s a f r e h t o r o f L E S V E D _ P e h t g n i r o t i n o m s a l l e w s a s s e r d d a e h t t r o p y r a m i r p e h t n o s e c i v e d m u i d e m d n a y r a m i r p n o r e t s a M y r a d n o c e s n o t e g r a T t i f i y l l a m r o n e l c...

Page 79: ...ust be checked for all addresses and write data Parity is defined on the P_PAR S1_PAR and S2_PAR signals Parityshouldbeeven i e anevennumberof 1 s acrossAD CBE andPAR ParityinformationonPARisvalidthecycle after AD and CBE are valid For reads even parity must be generated using the initiators CBE signals combined with the read data Again the PAR signal corresponds to read data from the previous dat...

Page 80: ...ing direct control and monitoring of processor pins at the system level This mode of operation is valuable for design debugging and fault diagnosis since it permits examination of connections not normally accessible to the test system The following subsections describe the boundary scan test logic elements TAPpins instructionregister testdataregistersandTAPcontroller Figure15 1illustrateshowthesep...

Page 81: ...r a d n u o b e h t s t c e n n o c t s e t x e y r t i u c r i c p i h c o t n i d e t f i h s s e u l a v y b n e v i r d e r a s e u l a v n i p l a n g i s t u p t u o l l a d e t c e l e s s i t s e t x E n e h W o s l A K C T f o e g d e g n i l l a f e h t n o y l n o e g n a h c y a m d n a r e t s i g e r n a c s y r a d n u o b e h t e h t o t n i d e d a o l e b t s u m s e t a t s n i ...

Page 82: ...ells configured in master slave stages and connectedbetweeneachofthePI7C7100 spinsandon chipsystemlogic TheVDD GND PLL AGND AVDDandJTAG pins are NOT in the boundary scan chain The boundary scan register cells are dedicated logic and do not have any system function Data may be loaded into the boundary scanregistermastercellsfromthedeviceinputpinsandoutputpin driversinparallelbythemandatorysample pr...

Page 83: ...A _ 2 S t u p n i 3 4 0 3 D A _ 2 S t u p t u o 4 4 0 3 D A _ 2 S t u p n i 5 4 1 3 D A _ 2 S t u p t u o 6 4 1 3 D A _ 2 S t u p n i 7 4 0 T N G _ 2 S e l b a n e l o r t n o c 8 4 0 T N G _ 2 S t u p t u o 9 4 0 Q E R _ 2 S t u p n i 0 5 1 Q E R _ 2 S t u p n i 1 5 1 T N G _ 2 S t u p t u o 2 5 2 T N G _ 2 S t u p t u o 3 5 2 Q E R _ 2 S t u p n i 4 5 3 Q E R _ 2 S t u p n i 5 5 3 T N G _ 2 S t ...

Page 84: ... 1 2 1 D A _ P t u p n i 9 4 1 8 D A _ P t u p t u o 0 5 1 8 D A _ P t u p n i 1 5 1 1 E B C _ P t u p t u o 2 5 1 1 E B C _ P t u p n i 3 5 1 9 D A _ P t u p t u o 4 5 1 9 D A _ P t u p n i 5 5 1 7 0 D A _ P e l b a n e l o r t n o c 6 5 1 5 D A _ P t u p t u o 7 5 1 5 D A _ P t u p n i 8 5 1 N E 6 6 M _ P t u p n i 9 5 1 6 D A _ P t u p t u o 0 6 1 6 D A _ P t u p n i 1 6 1 2 D A _ P t u p t u o...

Page 85: ...o 3 5 2 9 1 D A _ 1 S t u p n i 4 5 2 3 E B C _ 1 S t u p t u o 5 5 2 3 E B C _ 1 S t u p n i 6 5 2 3 2 D A _ 1 S t u p t u o 7 5 2 3 2 D A _ 1 S t u p n i 8 5 2 6 2 D A _ 1 S t u p t u o 9 5 2 6 2 D A _ 1 S t u p n i 0 6 2 2 2 D A _ 1 S t u p t u o 1 6 2 2 2 D A _ 1 S t u p n i 2 6 2 5 2 D A _ 1 S t u p t u o 3 6 2 5 2 D A _ 1 S t u p n i 4 6 2 9 2 D A _ 1 S t u p t u o 5 6 2 9 2 D A _ 1 S t u p ...

Page 86: ...i 8 2 3 4 1 D A _ 2 S t u p t u o 9 2 3 4 1 D A _ 2 S t u p n i 0 3 3 1 E B C _ 2 S t u p t u o 1 3 3 1 E B C _ 2 S t u p n i 2 3 3 5 1 D A _ 2 S t u p t u o 3 3 3 5 1 D A _ 2 S t u p n i 4 3 3 R A P _ 2 S e l b a n e l o r t n o c r e d r O s e m a N n i P e p y T 5 3 3 R A P _ 2 S t u p t u o 6 3 3 R A P _ 2 S t u p n i 7 3 3 R R E S _ 2 S t u p n i 8 3 3 K C O L _ 2 S e l b a n e l o r t n o c ...

Page 87: ... t i n U s e t o N V D D V A C C e g a t l o V y l p p u S 3 6 3 V V h i e g a t l o V H G I H t u p n I V 5 0 D D V D D 5 0 3 V l i e g a t l o V W O L t u p n I 5 0 3 0 V D D V h i e g a t l o V H G I H t u p n I S O M C V 7 0 D D V D D 5 0 1 V l i e g a t l o V W O L t u p n I S O M C 5 0 3 0 V D D V u p i e g a t l o V p u l l u P t u p n I V 7 0 D D 3 Il i t n e r r u C e g a k a e L t u p n ...

Page 88: ... m i t d l o h l a n g i s t u p n I 2 1 0 T l a v s l a n g i s d e s u b y a l e d d i l a v l a n g i s o t K L C 3 2 1 2 1 1 T p t p l a v t n i o p o t t n i o p y a l e d d i l a v l a n g i s o t K L C 3 2 1 2 2 1 T n o y a l e d e v i t c a o t t a o l F 2 1 2 T f f o y a l e d t a o l f o t e v i t c A 2 1 8 2 Vtest Tval Ton Th Valid Vtest 1 5V for 5V signals 0 4 VCC for 3 3V signals Vali...

Page 89: ...MATION PIN 1 CORNER 20 0 15 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y A 8 00 4 x 45 CHAMFER 2 33 Min 3 50Max 27 00 0 15 ø1 0 3X 0 60 0 1 3 0 2 SEATING PLANE 1 27 1 44 BSC 24 00 0 1 256 x ø0 75 0 15 0 56 0 05 1 17 0 1 0 30 S 0 10 S S S C C B B C C A 27 00 0 15 4X 17 256 Pin PBGA Package TOP BOTTOM 17 1 Part Number Ordering Information t r a P e g a k c ...

Page 90: ...67890121234567890123456789012345678901212345678901234567890123456789012123456 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 PI7C7100 3 Port PCI Bridge ADVANCE INFORMATION ...

Page 91: ...PI7C7100 3 Port PCI Bridge Appendix A Timing Diagrams ...

Page 92: ...01212345678901234567890123456789012123456789012345678901234567890121234 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234 Appendix A PI7C7100 3 Port PCI Bridge ADVANCE INFORMATION ...

Page 93: ... Figure 2 Configuration Write Transaction A Addr Data Byte Enables 0 1 2 3 4 5 6 7 8 9 10 11 12 P_CLK P_AD 31 0 P_CBE 3 0 P_FRAME_L P_IRDY_L P_TRDY_L P_STOP_L P_DEVSEL_L P_IDSEL 13 14 15 16 17 18 19 20 21 22 Figure 1 Configuration Read Transaction Addr Data Byte Enables A A Addr Byte Enables Addr Data Byte Enables A 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 0 1 2 3 4 5 6 7 8 9 10 ...

Page 94: ...9 20 21 22 P_CLK P_AD 31 0 P_CBE 3 0 P_FRAME_L P_IRDY_L P_TRDY_L P_STOP_L P_DEVSEL_L P_IDSEL S_CLKOUT 0 S_AD 31 0 S_CBE 3 0 S_FRAME_L S_IRDY_L S_TRDY_L S_STOP_L S_DEVSEL_L S_GNT_L S_REQ_L P_GNT_L P_REQ_L Figure 4 Type 1 to Type 0 Configuration Write Transaction P S Addr Data Addr Data Byte Enables Byte Enables B 1 B Addr Data Byte Enables Figure 5 Upstream Type 1 to Special Cycle Transaction S P 0...

Page 95: ...S_FRAME_L S_IRDY_L S_TRDY_L S_STOP_L S_DEVSEL_L S_GNT_L S_REQ_L P_GNT_L P_REQ_L Figure 6 Downstream Type 1 to Special Cycle Transaction P S Addr Addr BytesEnables B B Addr Addr Addr Data B B ByteEnables ByteEnables ByteEnables ByteEnables B Addr Addr Addr Data B B B ByteEnables ByteEnables ByteEnables Figure 7 Downstream Type1 to Type1 Configuration Read Transaction P S 0 2 4 6 8 10 12 14 16 18 20...

Page 96: ...32 34 36 38 40 42 44 45 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 P_CLK P_AD 31 0 P_CBE 3 0 P_FRAME_L P_IRDY_L P_TRDY_L P_STOP_L P_DEVSEL_L P_IDSEL S_CLKOUT 0 S_AD 31 0 S_CBE 3 0 S_FRAME_L S_IRDY_L S_TRDY_L S_STOP_L S_DEVSEL_L S_GNT_L S_REQ_L P_GNT_L P_REQ_L 6 Byte Enables Addr Data Data Data Data Data Data Data Data Addr Addr Addr 6 6 6 ByteEnables 6 Addr Data Data Data Data Da...

Page 97: ... 44 45 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 45 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 P_CLK P_AD 31 0 P_CBE 3 0 P_FRAME_L P_IRDY_L P_TRDY_L P_STOP_L P_DEVSEL_L S_CLKOUT 0 S_AD 31 0 S_CBE 3 0 S_FRAME_L S_IRDY_L S_TRDY_L S_STOP_L S_DEVSEL_L S_GNT_L S_REQ_L P_GNT_L P_REQ_L Addr Data Byte Enab...

Page 98: ...5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 S_CLKOUT 0 S1_AD 31 0 S1_CBE 3 0 S1_FRAME_L S1_IRDY_L S1_TRDY_L S1_STOP_L S1_DEVSEL_L S_CLKOUT 0 S2_AD 31 0 S2_CBE 3 0 S2_FRAME_L S2_IRDY_L S2_TRDY_L S2_STOP_L S2_DEVSEL_L S2_GNT_L S2_REQ_L S1_GNT_L S1_REQ_L 23 23 Addr Data Addr Data Byte Enables Byte Enables 6 6 6 Addr Byte Enables Figure 13 Downstream Delayed Memory Read Transaction S1 33MHz S2 33...

Page 99: ...4 15 16 17 18 19 20 21 22 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 P_CLK P_AD 31 0 P_CBE 3 0 P_FRAME_L P_IRDY_L P_TRDY_L P_STOP_L P_DEVSEL_L S_CLKOUT 0 S_AD 31 0 S_CBE 3 0 S_FRAME_L S_IRDY_L S_TRDY_L S_STOP_L S_DEVSEL_L S_GNT_L S_REQ_L P_GNT_L P_REQ_L 23 Data Byte Enables 7 Addr Data Byte Enables 7 Addr Figure 15 Downstream Posted Memory Write Transaction P 33MHz S 33MHz 0 1 2 3 ...

Page 100: ...2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 S_CLKOUT 0 S1_AD 31 0 S1_CBE 3 0 S1_FRAME_L S1_IRDY_L S1_TRDY_L S1_STOP_L S1_DEVSEL_L S_CLKOUT 0 S2_AD 31 0 S2_CBE 3 0 S2_FRAME_L S2_IRDY_L S2_TRDY_L S2_STOP_L S2_DEVSEL_L S2_GNT_L S2_REQ_L S1_GNT_L S1_REQ_L Addr Data Data Byte Enables Byte Enables 7 7 Addr Figure 17 Downstream Posted Memory Write Transaction S1 33MHz S2 33MHz 0 1 2 3 4 5 6 7 ...

Page 101: ... 15 16 17 18 19 20 21 22 P_CLK P_AD 31 0 P_CBE 3 0 P_FRAME_L P_IRDY_L P_TRDY_L P_STOP_L P_DEVSEL_L S_CLKOUT 0 S_AD 31 0 S_CBE 3 0 S_FRAME_L S_IRDY_L S_TRDY_L S_STOP_L S_DEVSEL_L S_GNT_L S_REQ_L P_GNT_L P_REQ_L Data Data Data Data Data Data Data Data Data Data Byte Enables 7 Addr Data Data Data Data Data Data Data Data Data Data Byte Enables 7 Addr Figure 19 Downstream Flow Through Posted Memory Wr...

Page 102: ... 11 12 13 14 15 16 17 18 19 20 21 22 S_CLKOUT 0 S1_AD 31 0 S1_CBE 3 0 S1_FRAME_L S1_IRDY_L S1_TRDY_L S1_STOP_L S1_DEVSEL_L S_CLKOUT 0 S2_AD 31 0 S2_CBE 3 0 S2_FRAME_L S2_IRDY_L S2_TRDY_L S2_STOP_L S2_DEVSEL_L S2_GNT_L S2_REQ_L S1_GNT_L S1_REQ_L 23 24 25 23 24 25 Addr Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Byte Enables Byte Enables 7 7 Ad...

Page 103: ...11 12 13 14 15 16 17 18 19 20 21 22 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 P_CLK P_AD 31 0 P_CBE 3 0 P_FRAME_L P_IRDY_L P_TRDY_L P_STOP_L P_DEVSEL_L S_CLKOUT 0 S_AD 31 0 S_CBE 3 0 S_FRAME_L S_IRDY_L S_TRDY_L S_STOP_L S_DEVSEL_L S_GNT_L S_REQ_L P_GNT_L P_REQ_L 23 24 25 26 27 28 23 24 25 26 27 28 Addr Data Byte Enables 2 2 Addr Byte Enables Addr Data Byte Enables 2 0 1 2 3 4 5 6 ...

Page 104: ...5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 S_CLKOUT 0 S1_AD 31 0 S1_CBE 3 0 S1_FRAME_L S1_IRDY_L S1_TRDY_L S1_STOP_L S1_DEVSEL_L S_CLKOUT 0 S2_AD 31 0 S2_CBE 3 0 S2_FRAME_L S2_IRDY_L S2_TRDY_L S2_STOP_L S2_DEVSEL_L S2_GNT_L S2_REQ_L S1_GNT_L S1_REQ_L 23 23 Addr Data Addr Data Byte Enables Byte Enables 2 2 2 Addr Byte Enables Figure 25 Downstream Delayed I O Read Transaction S1 33MHz S2 33MHz...

Page 105: ... 17 18 19 20 21 22 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 P_CLK P_AD 31 0 P_CBE 3 0 P_FRAME_L P_IRDY_L P_TRDY_L P_STOP_L P_DEVSEL_L S_CLKOUT 0 S_AD 31 0 S_CBE 3 0 S_FRAME_L S_IRDY_L S_TRDY_L S_STOP_L S_DEVSEL_L S_GNT_L S_REQ_L P_GNT_L P_REQ_L 23 Addr Data Byte Enables 3 3 Addr Data Byte Enables Addr Data Byte Enables 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 ...

Page 106: ...5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 S_CLKOUT 0 S1_AD 31 0 S1_CBE 3 0 S1_FRAME_L S1_IRDY_L S1_TRDY_L S1_STOP_L S1_DEVSEL_L S_CLKOUT 0 S2_AD 31 0 S2_CBE 3 0 S2_FRAME_L S2_IRDY_L S2_TRDY_L S2_STOP_L S2_DEVSEL_L S2_GNT_L S2_REQ_L S1_GNT_L S1_REQ_L 23 23 Addr Data Addr Data Byte Enables Byte Enables 3 3 3 Addr Data Byte Enables Figure 29 Downstream Delayed I O Write Transaction S1 33MHz S2...

Page 107: ...C7100 3 Port PCI Bridge ADVANCE INFORMATION Addr Data Addr Data Byte Enables Byte Enables 3 3 3 Addr Data Byte Enables Figure 30 Upstream Delayed I O Write Transaction S P 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 P_CLK P_AD 31 0 P_CBE 3 0 P_FRAME_L P_IRDY_L P_TRDY_L P_STOP_L P_DEVSEL_L S_CLKOUT 0 S_AD 31 0 S_CBE 3 0 S_FRA...

Page 108: ...01212345678901234567890123456789012123456789012345678901234567890121234 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234 Appendix A PI7C7100 3 Port PCI Bridge ADVANCE INFORMATION ...

Page 109: ...PI7C7100 3 Port PCI Bridge AppendixB Evaluation Board User s Manual ...

Page 110: ...21234567890123456789012345678901212345678901234567890123456789012123456 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 Appendix B PI7C7100 3 Port PCI Bridge ADVANCE INFORMATION ...

Page 111: ...V and 12V and ground 4 Plug evaluation board in any PCI slot on your system Make sure your system is powered off before doing so 5 Connect any PCI devices on the secondary slots of the evaluation board Be careful that the orientation of the card is correct see Diagram A e m a N n i P r e p m u J n o i t c n u F n o i t i s o P N F C _ S 4 P J e l b a n e r e t i b r a l a n r e t n I 0 2 1 N E _ 1...

Page 112: ...rs for the PI7C7100 evaluation board In Win9X Plug and Play should detect the device as a PCI to PCI bridge The system may prompt you for the Win9X CD for the drivers The OS will detect two PCI to PCI bridges as the PI7C7100 has two secondary PCI buses In Win NT you should not have to install drivers 7 Install drivers for any PCI devices you have attached to the evaluation board 8 If any of the st...

Page 113: ...uired for normal operation The following table indicates which bus signals correspond to which pins 5 What is the purpose for having U17 U19 and U20 U17 U19 and U20 are designed for easy access to the digital ground planes for observation 6 How is the evaluation board constructed The evaluation board is a six layer PCB The top and bottom layers 1 and 6 are for signals power and ground routing Laye...

Page 114: ...21234567890123456789012345678901212345678901234567890123456789012123456 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 Appendix B PI7C7100 3 Port PCI Bridge ADVANCE INFORMATION ...

Page 115: ...PI7C7100 3 Port PCI Bridge AppendixC Schematics ...

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Page 117: ...00 P_AD 0 R17 P_AD 1 T17 P_AD 2 Y20 P_AD 3 V20 P_AD 4 U20 P_AD 5 Y19 P_AD 6 W19 P_AD 7 U19 P_AD 8 Y18 P_AD 9 W18 P_AD 10 U18 P_AD 11 Y17 P_AD 12 W17 P_AD 13 Y16 P_AD 14 W16 P_AD 25 Y9 P_AD 16 V12 P_AD 17 W12 P_AD 18 Y12 P_AD 19 U11 P_AD 20 V11 P_AD 21 Y11 P_AD 22 V10 P_AD 23 W10 P_AD 24 W9 P_AD 15 V16 P_AD 26 U8 P_AD 27 V8 P_AD 28 W8 P_AD 29 Y8 P_AD 30 W7 P_AD 31 Y7 P_CBE 0 V19 P_CBE 1 U16 P_CBE 2...

Page 118: ...38 1header T 1 C113 0 1uF C114 0 1uF C115 0 01uF C116 0 01uF C1 0 1uF C6 0 001uF C14 0 001uF C15 0 001uF C18 0 001uF JP1 HEADER 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 JP2 HEADER 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 JP3 HEADER 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 U5 PCIEDGE TRST A1 12V A2 TMS A3 TDI A4 5V A5 INTA A6 INTC A7 5V A8 NC A9 5VIO1 A10 NC A11 NC A14 RST A15 5VIO1 A16 GNT A17 ...

Page 119: ...B61 5V B62 U9 PCISLOT TRST A1 12V A2 TMS A3 TDI A4 5V A5 INTA A6 INTC A7 5V A8 NC A9 5V A10 NC A11 GND A12 GND A13 NC A14 RST A15 5V A16 GNT A17 GND A18 NC A19 AD30 A20 3 3V A21 AD28 A22 AD26 A23 GND A24 AD24 A25 IDSEL A26 3 3V A27 AD22 A28 AD20 A29 GND A30 AD18 A31 AD16 A32 3 3V A33 FRAME A34 GND A35 TRDY A36 GND A37 STOP A38 3 3V A39 SDONE A40 SBO A41 GND A42 PAR A43 AD15 A44 3 3V A45 AD13 A46 A...

Page 120: ...18 NC A19 AD30 A20 3 3V A21 AD28 A22 AD26 A23 GND A24 AD24 A25 IDSEL A26 3 3V A27 AD22 A28 AD20 A29 GND A30 AD18 A31 AD16 A32 3 3V A33 FRAME A34 GND A35 TRDY A36 GND A37 STOP A38 3 3V A39 SDONE A40 SBO A41 GND A42 PAR A43 AD15 A44 3 3V A45 AD13 A46 AD11 A47 GND A48 AD09 A49 NC A50 NC A51 C BE0 A52 3 3V A53 AD06 A54 AD04 A55 GND A56 AD02 A57 AD00 A58 5V A59 REQ64 A60 5V A61 5V A62 12V B1 TCK B2 GND...

Page 121: ...EL_L P_SERR_L S1_FRAME_L P_C BE 3 0 S1_LOCK_L S2_REQN 7 0 TMS P_GNT_L PLL_CAP1 S2_PAR_L P_IRDY_L P_STOP_ L S2_FRAME_L S1_SERR_L P_IDSEL_L TCK TDI S_M66EN S2_PAR_L S2_TRDY_L S2_SERR_L TDO P_LOCK_L S1_LOCK_L TDO P_FRAME_L P_PAR_L P_REQ_L P_TRDY_L P_M66EN TRST_L S1_RESET_ L S1_DEVSEL_ L P_REQ_L P_CLK S1_REQN 7 0 S1_TRDY_L S1_IRDY_L S1_IRDY_L S1_TRDY_L S1_IDSEL0_L S1_IDSEL1_L S1_IDSEL2_L S1_IDSEL3_L S...

Page 122: ...21234567890123456789012345678901212345678901234567890123456789012123456 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 Appendix C PI7C7100 3 Port PCI Bridge ADVANCE INFORMATION ...

Page 123: ...89012123456789012345678901234567890121234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 PI7C7100 3 Port PCI Bridge ADVANCE INFORMATION PI7C7100 3 Port PCI Bridge AppendixD Representatives Distributors ...

Page 124: ... 27511 USA 919 460 3177 919 460 3179 Fax mward pericom com North East and Mid and Eastern Canada Pericom Semiconductor Corp Radnor Station Building 2 290 King of Prussia Road Suite 104 Radnor PA 19087 610 293 7400 610 293 7410 Fax gfrancisco pericom com Europe Pericom Semiconductor Corp The Enterprise Center 1 2 Davy Road Gorse Lane Industrial Center Clacton On Sea Essex UK CO15 4XD 44 1255 479994...

Page 125: ...6783 7877 916 783 7988 Future 5990StoneridgeDrive Pleasanton CA 94588 USA 925225 0294 925225 9745 Future 6256GreenwichDrive Suite200 SanDiego CA 92122 USA 858 625 2800 858 625 2810 NuHorizons 1220MelodyLane Suite110 Roseville CA 95678 USA 916783 5500 916 783 3066 NuHorizons 13900AltonParkway Suite123 Irvine CA 92718 USA 949470 1011 949 470 1104 NuHorizons 2070RingwoodAvenue SanJose CA 95131 USA 40...

Page 126: ...tryClubDrive Suite100 Famingron Hills MI 48331 USA 248489 1179 248 489 1030 Future 4595BroadmoorSE Suite280 GrandRapids MI 49512 USA 616534 3510 616 698 6821 Pioneer StandardElectronics 44190PlymouthOaksBlvd Plymouth MI 48170 USA 734 416 2157 734 416 2415 Pioneer StandardElectronics 4476ByronCenterRoadSW GrandRapids MI 49509 USA 616 534 3145 616 534 3922 AllAmerican 6608FlyingCloudDrive EdenPrairi...

Page 127: ...238 USA 412782 2300 412 963 8255 AllAmerican 13706ResearchBlvd Suite103 Austin TX 78750 USA 512335 2280 512335 2282 AllAmerican 1771InternationalParkway Suite101 Richardson TX 75081 USA 972231 5300 972437 0353 BellMicroproducts 12701ResearchBlvd Suite360 Austin TX 78759 USA 512258 0725 512 258 6517 BellMicroproducts 833EastAraphhoRoad Suite205 Richardson TX 75081 USA 972783 4191 972 783 4192 BellM...

Page 128: ...44752HelmStreet Plymouth MI 48170 USA 734 459 1200 734 459 1697 Cahill Schmitz Cahill Inc 897St PaulAvenue St Paul MN 55116 USA 6516990200 651 699 0800 Martan Inc 257OldStoneCourt O Fallon MO 63366 USA 3149393300 314 447 1371 BITS Inc 940MainCampusDrive Suite120 Raleigh NC 27606 USA 9198071000 919 807 1001 BITS Inc 3320SilverPondCourt Charlotte NC 28810 USA 704 540 8185 704 540 8183 MatrixSales 30...

Page 129: ...ow G8112RX UK 0419511199 Future Urb BelmonteGalicia 45 Mayaguez 00680 PuertoRico 787289 7801 Future ViaFosseArdeatine4 20092CiniselloBalsamo Milan ITALY 392660941 Future Wilhelm WolffStr 6 Erfurt 99099 GERMANY 0361420870 FutureElectronicsOY Olarinluoma7 Fon 02200 Espoo Helsinki FINLAND 01135895259950 FutureElectronics Distribution Spain S L AvenidaD dek Oarebib8 10 Madrid SPAIN 3417210762 FutureEl...

Page 130: ...ien24 Fjellhamar 1472 NORWAY 47 67 90 52 44 Hy LineComputerComponents Inselkammerstrasse10 Unterhaching 82008 GERMANY 011 49 89 614503 40 I CMicrosystems Co Ltd 8thFloor BethelBldg 324 1 Yangjae Dong Seocho Ku SEOUL KOREA 82 2 577 9131 InternixInc HachiojiBranch 59 10Takakura cho Hachioji shi Tokyo 192 0033 JAPAN 81 426 448786 InternixInc HeadOffice ShinjukuHamadaBldg 3F7 4 7 Nishishinjuku Shinjuk...

Page 131: ...01212345678901234567890123456789012123456789012345678901234567890121234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 PI7C7100 3 Port PCI Bridge ADVANCE INFORMATION NOTES ...

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