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09/18/00 Rev 1.1
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PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
I/O transactions with addresses that fall inside the range defined by the I/O base and limit registers are forwarded
downstream from the primary PCI bus to the secondary PCI bus. I/O transactions with addresses that fall outside this
range are forwarded upstream from the secondary PCI bus to the primary PCI bus.
The I/O range can be turned off by setting the I/O base address to a value greater than that of the I/O limit address. When
the I/O range is turned off, all I/O transactions are forwarded upstream, and no I/O transactions are forwarded
downstream. The I/O range has a minimum granularity of 4KB and is aligned on a 4KB boundary. The maximum I/O
range is 4GB in size. The I/O base register consists of an 8-bit field at configuration address 1Ch, and a 16-bit field at
address 30h. The top 4 bits of the 8-bit field define bits [15:12] of the I/O base address. The bottom 4 bits read only as
1h to indicate that PI7C7100 supports 32-bit I/O addressing. Bits [11:0] of the base address are assumed to be 0, which
naturally aligns the base address to a 4KB boundary. The 16 bits contained in the I/O base upper 16 bits register at
configuration offset 30h define AD[31:16] of the I/O base address. All 16 bits are read/write. After primary bus reset or
chip reset, the value of the I/O base address is initialized to 0000 0000h.
The I/O limit register consists of an 8-bit field at configuration offset 1Dh and a 16-bit field at offset 32h. The top 4 bits
of the 8-bit field define bits [15:12] of the I/O limit address. The bottom 4 bits read only as 1h to indicate that 32-bit I/O
addressing is supported. Bits [11:0] of the limit address are assumed to be FFFh, which naturally aligns the limit address
to the top of a 4KB I/O address block. The 16 bits contained in the I/O limit upper 16 bits register at configuration offset
32h define AD[31:16] of the I/O limit address. All 16 bits are read/write. After primary bus reset or chip reset, the value
of the I/O limit address is reset to 0000 0FFFh.
Note: The initial states of the I/O base and I/O limit address registers define an I/O range of 0000 0000h to 0000 0FFFh,
which is the bottom 4KB of I/O space. Write these registers with their appropriate values before setting either the I/O enable
bit or the master enable bit in the command register in configuration space.
5.2.2 ISA Mode
PI7C7100 supports ISA mode by providing an ISA enable bit in the bridge control register in configuration space. ISA mode
modifies the response of PI7C7100 inside the I/O address range in order to support mapping of I/O space in the presence
of an ISA bus in the system. This bit only affects the response of PI7C7100 when the transaction falls inside the address
range defined by the I/O base and limit address registers, and only when this address also falls inside the first 64KB of
I/O space (address bits [31:16] are 0000h).
When the ISA enable bit is set, PI7C7100 does not forward downstream any I/O transactions addressing the top 768 bytes
of each aligned 1KB block. Only those transactions addressing the bottom 256 bytes of an aligned 1KB block inside the
base and limit I/O address range are forwarded downstream. Transactions above the 64KB I/O address boundary are
forwarded as defined by the address range defined by the I/O base and limit registers.
Accordingly, if the ISA enable bit is set, PI7C7100 forwards upstream those I/O transactions addressing the top 768 bytes
of each aligned 1KB block within the first 64KB of I/O space. The master enable bit in the command configuration register
must also be set to enable upstream forwarding. All other I/O transactions initiated on the secondary bus are forwarded
upstream only if they fall outside the I/O address range.
When the ISA enable bit is set, devices downstream of PI7C7100 can have I/O space mapped into the first 256 bytes of
each 1KB chunk below the 64KB boundary, or anywhere in I/O space above the 64KB boundary.
5.3 Memory Address Decoding
PI7C7100 has three mechanisms for defining memory address ranges for forwarding of memory transactions:
• Memory-mapped I/O base and limit address registers
• Prefetchable memory base and limit address registers
• VGA mode
This section describes the first two mechanisms. Section 5.4.1 describes VGA mode.
To enable downstream forwarding of memory transactions, the memory enable bit must be set in the command register
in configuration space. To enable upstream forwarding of memory transactions, the master-enable bit must be set in
the command register. The master-enable bit also allows upstream forwarding of I/O transactions if it is set.
