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09/18/00 Rev 1.1
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PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
7.2.2 Read Transactions
When PI7C7100 detects a parity error during a read transaction, the target drives data and data parity, and the initiator
checks parity and conditionally asserts PERR#.
For downstream transactions, when PI7C7100 detects a read data parity error on the secondary bus, the following events
occur:
•
PI7C7100 asserts S_PERR# two cycles following the data transfer, if the secondary interface parity error re-
sponse bit is set in the bridge control register.
•
PI7C7100 sets the detected parity error bit in the secondary status register.
•
PI7C7100 sets the data parity detected bit in the secondary status register, if the secondary interface parity error
response bit is set in the bridge control register.
•
PI7C7100 forwards the bad parity with the data back to the initiator on the primary bus.
If the data with the bad parity is pre-fetched and is not read by the initiator on the primary bus, the data is
discarded and the data with bad parity is not returned to the initiator.
•
PI7C7100 completes the transaction normally.
For upstream transactions, when PI7C7100 detects a read data parity error on the primary bus, the following events occur:
•
PI7C7100 asserts P_PERR# two cycles following the data transfer, if the primary interface parity error
response bit is set in the command register.
•
PI7C7100 sets the detected parity error bit in the primary status register.
•
PI7C7100 sets the data parity detected bit in the primary status register, if the primary interface parity-error-
response bit is set in the command register.
•
PI7C7100 forwards the bad parity with the data back to the initiator on the secondary bus.
If the data with the bad parity is pre-fetched and is not read by the initiator on the secondary bus, the data is
discarded and the data with bad parity is not returned to the initiator.
•
PI7C7100 completes the transaction normally.
PI7C7100 returns to the initiator the data and parity that was received from the target. When the initiator detects
a parity error on this read data and is enabled to report it, the initiator asserts PERR# two cycles after the data
transfer occurs. It is assumed that the initiator takes responsibility for handling a parity error condition; therefore,
when PI7C7100 detects PERR# asserted while returning read data to the initiator, PI7C7100 does not take any
further action and completes the transaction normally.
7.2.3 Delayed Write Transactions
When PI7C7100 detects a data parity error during a delayed write transaction, the initiator drives data and data parity,
and the target checks parity and conditionally asserts PERR#.
For delayed write transactions, a parity error can occur at the following times:
•
During the original delayed write request transaction
•
When the initiator repeats the delayed write request transaction
•
When PI7C7100 completes the delayed write transaction to the target
When a delayed write transaction is normally queued, the address, command, address parity, data, byte enable bits,
and data parity are all captured and a target retry is returned to the initiator. When PI7C7100 detects a parity error on
the write data for the initial delayed write request transaction, the following events occur:
•
If the parity-error-response bit corresponding to the initiator bus is set, PI7C7100 asserts TRDY# to the initiator
and the transaction is not queued. If multiple data phases are requested, STOP# is also asserted to cause a
target disconnect. Two cycles after the data transfer, PI7C7100 also asserts PERR#.
If the parity-error-response bit is not set, PI7C7100 returns a target retry. It queues the transaction as usual.
PI7C7100 does not assert PERR#. In this case, the initiator repeats the transaction.
•
PI7C7100 sets the detected-parity-error bit in the status register corresponding to the initiator bus, regardless
of the state of the parity-error-response bit.
