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09/18/00 Rev 1.1
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PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
7. Error Handling
PI7C7100 checks, forwards, and generates parity on both the primary and secondary interfaces. To maintain
transparency, PI7C7100 always tries to forward the existing parity condition on one bus to the other bus, along with address
and data. PI7C100 always attempts to be transparent when reporting errors, but this is not always possible, given the
presence of posted data and delayed transactions.
To support error reporting on the PCI bus, PI7C7100 implements the following:
•
PERR# and SERR# signals on both the primary and secondary interfaces
•
Primary status and secondary status registers
•
The device-specific P_SERR# event disable register
This chapter provides detailed information about how PI7C7100 handles errors. It also describes error status reporting
and error operation disabling.
7.1 Address Parity Errors
PI7C7100 checks address parity for all transactions on both buses, for all address and all bus commands. When
PI7C7100 detects an address parity error on the primary interface, the following events occur:
• If the parity error response bit is set in the command register, PI7C7100 does not claim the transaction with
P_DEVSEL#; this may allow the transaction to terminate in a master abort.
If parity error response bit is not set, PI7C7100 proceeds normally and accepts the transaction if it is directed to or
across PI7C7100.
• PI7C7100 sets the detected parity error bit in the status register.
• PI7C7100 asserts P_SERR# and sets signaled system error bit in the status register, if both the following conditions
are met:
- The SERR# enable bit is set in the command register.
- The parity error response bit is set in the command register.
When PI7C7100 detects an address parity error on the secondary interface, the following events occur:
• If the parity error response bit is set in the bridge control register, PI7C7100 does not claim the transaction with
S1_DEVSEL# or S2_DEVSEL#; this may allow the transaction to terminate in a master abort. If parity error
response bit is not set, PI7C7100 proceeds normally and accepts transaction if it is directed to or across PI7C7100.
• PI7C7100 sets the detected parity error bit in the secondary status register.
• PI7C7100 asserts P_SERR# and sets signaled system error bit in status register, if both of the following
conditions are met:
- The SERR# enable bit is set in the command register.
- The parity error response bit is set in the bridge control register.
7.2 Data Parity Errors
When forwarding transactions, PI7C7100 attempts to pass the data parity condition from one interface to the other
unchanged, whenever possible, to allow the master and target devices to handle the error condition.
The following sections describe, for each type of transaction, the sequence of events that occurs when a parity error is
detected and the way in which the parity condition is forwarded across PI7C7100.
7.2.1 Configuration Write Transactions to Configuration Space
When PI7C7100 detects a data parity error during a Type 0 configuration write transaction to PI7C7100 configuration
space, the following events occur:
• If the parity error response bit is set in the command register, PI7C7100 asserts P_TRDY# and writes the data to
the configuration register. PI7C7100 also asserts P_PERR#. If the parity error response bit is not set, PI7C7100
does not assert P_PERR#.
• PI7C7100 sets the detected parity error bit in the status register, regardless of the state of the parity error response bit.
