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09/18/00 Rev 1.1
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PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
The target can terminate transactions with one of the following types of termination:
• Normal termination—TRDY# and DEVSEL# asserted in conjunction with FRAME# de-asserted and IRDY# asserted.
• Target retry—STOP# and DEVSEL# asserted with TRDY# de-asserted during the first data phase. No data transfers
occur during the transaction. This transaction must be repeated.
• Target disconnect with data transfer—STOP#, DEVSEL# and TRDY# asserted. It signals that this is the last data
transfer of the transaction.
• Target disconnect without data transfer—STOP# and DEVSEL# asserted with TRDY# de-asserted after previous
data transfers have been made. Indicates that no more data transfers will be made during this transaction.
• Target abort—STOP# asserted with DEVSEL# and TRDY# de-asserted.
Indicates that target will never be able to complete this transaction. DEVSEL# must be asserted for at least one cycle
during the transaction before the target abort is signaled.
4.8.1 Master Termination Initiated by PI7C7100
PI7C7100, as an initiator, uses normal termination if DEVSEL# is returned by target within five clock cycles of PI7C7100’s
assertion of FRAME# on the target bus. As an initiator, PI7C7100 terminates a transaction when the following conditions are
met:
• During a delayed write transaction, a single DWORD is delivered.
• During a non-prefetchable read transaction, a single DWORD is transferred from the target.
• During a prefetchable read transaction, a pre-fetch boundary is reached.
• For a posted write transaction, all write data for the transaction is transferred from data buffers to the target.
• For burst transfer, with the exception of “Memory Write and Invalidate” transactions, the master latency timer
expires and the PI7C7100’s bus grant is de-asserted.
• The target terminates the transaction with a retry, disconnect, or target abort.
If PI7C7100 is delivering posted write data when it terminates the transaction because the master latency timer
expires, it initiates another transaction to deliver the remaining write data. The address of the transaction is updated
to reflect the address of the current DWORD to be delivered.
If PI7C7100 is pre-fetching read data when it terminates the transaction because the master latency timer expires, it
does not repeat the transaction to obtain more data.
4.8.2 Master Abort Received by PI7C7100
If the initiator initiates a transaction on the target bus and does not detect DEVSEL# returned by the target within five clock
cycles of the assertion of FRAME#, PI7C7100 terminates the transaction with a master abort. This sets the received-
master-abort bit in the status register corresponding to the target bus.
For delayed read and write transactions, PI7C7100 is able to reflect the master abort condition back to the initiator. When
PI7C7100 detects a master abort in response to a delayed transaction, and when the initiator repeats the transaction,
PI7C7100 does not respond to the transaction with DEVSEL# which induces the master abort condition back to the
initiator. The transaction is then removed from the delayed transaction queue. When a master abort is received in
response to a posted write transaction, PI7C7100 discards the posted write data and makes no more attempt to deliver
the data. PI7C7100 sets the received-master-abort bit in the status register when the master abort is received on the
primary bus, or it sets the received master abort bit in the secondary status register when the master abort is received
on the secondary interface. When master abort is detected in posted write transaction with both master-abort-mode bit
(bit 5 of bridge control register) and the SERR# enable bit (bit 8 of command register for secondary bus S1 or S2) are
set, PI7C7100 asserts P_SERR# if the master-abort-on-posted-write is not set. The master-abort-on-posted-write bit
is bit 4 of the P_SERR# event disable register (offset 64h).
Note: When PI7C7100 performs a Type 1 to special cycle conversion, a master abort is the expected termination for the
special cycle on the target bus. In this case, the master abort received bit is not set, and the Type 1 configuration
transaction is disconnected after the first data phase.
