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PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
4.6.4 Delayed Read Requests
PI7C7100 treats all read transactions as delayed read transactions, which means that the read request from the initiator
is posted into a delayed transaction queue. Read data from the target is placed in the read data queue directed toward
the initiator bus interface and is transferred to the initiator when the initiator repeats the read transaction.
When PI7C7100 accepts a delayed read request, it first samples the read address, read bus command, and address parity.
When IRDY# is asserted, PI7C7100 then samples the byte enable bits for the first data phase. This information is entered
into the delayed transaction queue. PI7C7100 terminates the transaction by signaling a target retry to the initiator. Upon
reception of the target retry, the initiator is required to continue to repeat the same read transaction until at least one data
transfer is completed, or until a target response (target abort or master abort) other than a target retry is received.
4.6.5 Delayed Read Completion with Target
When delayed read request reaches the head of the delayed transaction queue, PI7C7100 arbitrates for the target bus
and initiates the read transaction only if all previously queued posted write transactions have been delivered. PI7C7100
uses the exact read address and read command captured from the initiator during the initial delayed read request to initiate
the read transaction. If the read transaction is a non-prefetchable read, PI7C7100 drives the captured byte enable bits
during the next cycle. If the transaction is a prefetchable read transaction, it drives all byte enable bits to zero for all data
phases. If PI7C7100 receives a target retry in response to the read transaction on the target bus, it continues to repeat
the read transaction until at least one data transfer is completed, or until an error condition is encountered. If the transaction
is terminated via normal master termination or target disconnect after at least one data transfer has been completed,
PI7C7100 does not initiate any further attempts to read more data.
If PI7C7100 is unable to obtain read data from the target after 2
24
(default) or 2
32
(maximum) attempts, PI7C7100 will report
system error. The number of attempts is programmable. PI7C7100 also asserts P_SERR# if the primary SERR# enable
bit is set in the command register. See Section 7.4 for information on the assertion of P_SERR#.
Once PI7C7100 receives DEVSEL# and TRDY# from the target, it transfers the data read to the opposite direction read
data queue, pointing toward the opposite interface, before terminating the transaction. For example, read data in response
to a downstream read transaction initiated on the primary bus is placed in the upstream read data queue. The PI7C7100
can accept one DWORD of read data each PCI clock cycle; that is, no master wait states are inserted. The number of
DWORD transferred during a delayed read transaction depends on the conditions given in Table 4–5 (assuming no
disconnect is received from the target).
4.6.6 Delayed Read Completion on Initiator Bus
When the transaction has been completed on the target bus, and the delayed read data is at the head of the read data
queue, and all ordering constraints with posted write transactions have been satisfied, the PI7C7100 transfers the data
to the initiator when the initiator repeats the transaction. For memory read transactions, PI7C7100 aliases the memory
read, memory read line, and memory read multiple bus commands when matching the bus command of the transaction
to the bus command in the delayed transaction queue. PI7C7100 returns a target disconnect along with the transfer of
the last DWORD of read data to the initiator. If PI7C7100 initiator terminates the transaction before all read data has been
transferred, the remaining read data left in data buffers is discarded.
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Table 4-5. Read Transaction Pre-Fetching
See Section 5.3 for detailed information about prefetchable and non-prefetchable address spaces.
