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09/18/00 Rev 1.1
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PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
For upstream transactions, when the parity error is being passed back from the target bus and the parity error condition
was not originally detected on the initiator bus, the following events occur:
•
PI7C7100 asserts S_PERR# two cycles after the data transfer, if the following are both true:
- The parity error response bit is set in the command register of the primary interface.
- The parity error response bit is set in the bridge control register of the secondary interface.
•
PI7C7100 completes the transaction normally.
7.2.4 Posted Write Transactions
During downstream posted write transactions, when PI7C7100 responds as a target, it detects a data parity error on the
initiator (primary) bus, the following events occur:
•
PI7C7100 asserts P_PERR# two cycles after the data transfer, if the parity error response bit is set in the
command register of primary interface.
•
PI7C7100 sets the parity error detected bit in the status register of the primary interface.
•
PI7C7100 captures and forwards the bad parity condition to the secondary bus.
•
PI7C7100 completes the transaction normally.
Similarly, during upstream posted write transactions, when PI7C7100 responds as a target, it detects a data parity error
on the initiator (secondary) bus, the following events occur:
•
PI7C7100 asserts S_PERR# two cycles after the data transfer, if the parity error response bit is set in the bridge
control register of the secondary interface.
•
PI7C7100 sets the parity error detected bit in the status register of the secondary interface.
•
PI7C7100 captures and forwards the bad parity condition to the primary bus.
•
PI7C7100 completes the transaction normally.
During downstream write transactions, when a data parity error is reported on the target (secondary) bus by the target’s
assertion of S_PERR#, the following events occur:
•
PI7C7100 sets the data parity detected bit in the status register of secondary interface, if the parity error
response bit is set in the bridge control register of the secondary interface.
•
PI7C7100 asserts P_SERR# and sets the signaled system error bit in the status register, if all the following
conditions are met:
- The SERR# enable bit is set in the command register.
- The posted write parity error bit of P_SERR# event disable register is not set.
- The parity error response bit is set in the bridge control register of the secondary interface.
- The parity error response bit is set in the command register of the primary interface.
- PI7C7100 has not detected the parity error on the primary (initiator) bus which the parity error is not forwarded
from the primary bus to the secondary bus.
During upstream write transactions, when a data parity error is reported on the target (primary) bus by the target’s assertion
of P_PERR#, the following events occur:
•
PI7C7100 sets the data parity detected bit in the status register, if the parity error response bit is set in the
command register of the primary interface.
•
PI7C7100 asserts P_SERR# and sets the signaled system error bit in the status register, if all the following
conditions are met:
- The SERR# enable bit is set in the command register.
- The parity error response bit is set in the bridge control register of the secondary interface.
- The parity error response bit is set in the command register of the primary interface.
- PI7C7100 has not detected the parity error on the secondary (initiator) bus which the parity error is not
forwarded from the secondary bus to the primary bus.
Assertion of P_SERR# is used to signal the parity error condition when the initiator does not know that the error occurred.
