Penguin Computing Relion 1900e, Technical Manual

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Relion 1900e/2900e Manual
Revision 1.0 66
The BMC supports one IPMI processor (margin) temperature sensor per physical processor package. This
sensor aggregates the readings of the individual core temperatures in a package to provide the hottest core
temperature reading. When the sensor reads ‘0’, it indicates that the hottest processor core is throttling.
Due to the fact that the readings are capped at the core’s thermal throttling trip point (reading = 0),
thresholds are not set and alert generation is not enabled for these sensors.
7.3.10.4 Processor Thermal Control Monitoring (Prochot)
The BMC FW monitors the percentage of time that a processor has been operationally constrained over a
given time window (nominally six seconds) due to internal thermal management algorithms engaging to
reduce the temperature of the device. When any processor core temperature reaches its maximum operating
temperature, the processor package PROCHOT# (processor hot) signal is asserted and these management
algorithms, known as the Thermal Control Circuit (TCC), engage to reduce the temperature, provided TCC is
enabled. TCC is enabled by BIOS during system boot. This monitoring is instantiated as one IPMI
analog/threshold sensor per processor package. The BMC implements this as a threshold sensor on a per-
processor basis.
Under normal operation, this sensor is expected to read ‘0’ indicating that no processor throttling has
occurred.
The processor provides PECI-accessible counters, one for the total processor time elapsed and one for the
total thermally constrained time, which are used to calculate the percentage assertion over the given time
window.
7.3.10.5 Processor Voltage Regulator (VRD) Over-Temperature Sensor
The BMC monitors processor VRD_HOT# signals. The processor VRD_HOT# signals are routed to the
respective processor PROCHOT# input in order to initiate throttling to reduce processor power draw,
therefore indirectly lowering the VRD temperature.
There is one processor VRD_HOT# signal per CPU slot.
The memory VRD_HOT# signals are routed to the respective processor MEMHOT# inputs in order to throttle
the associated memory to effectively lower the temperature of the VRD feeding that memory. For Intel®
Server Systems supporting the Intel® Xeon® processor E5-2600 v3, v4 product family there are 2 memory
VRD_HOT# signals per CPU slot.
The BMC instantiates one discrete IPMI sensor for each processor and memory VRD_HOT# signal.
7.3.10.6 Inlet Temperature Sensor
Each platform supports a thermal sensor for monitoring the inlet temperature. In most cases, ME firmware
will issue Get Sensor Reading IPMI command to the BMC to get the Inlet temperature. ME firmware
determines which of the BMC thermal sensors to use for inlet temperature. For Intel® chassis, the inlet
temperature sensor is on HSBP with address 21h. For 3rd chassis, sensor 20h which is on the front edge of
baseboard can be used as inlet temperature sensor with several degrees offset from actual inlet
temperature.
7.3.10.7 Baseboard Ambient Temperature Sensor(s)
The server baseboard provides one or more physical thermal sensors for monitoring the ambient
temperature of a board location. This is typically to provide rudimentary thermal monitoring of components
that lack internal thermal sensors.