Penguin Computing Relion 1900e, Technical Manual

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Relion 1900e/2900e Manual
Revision 1.0 22
4.2 IMC Modes of operation
A memory controller can be configured to operate in one of two modes, and each IMC operates separately.
Independent Mode: This is also known as performance mode. In this mode each DDR channel is addressed
individually via burst lengths of 8 bytes.

All processors support SECDED ECC with x8 DRAMs in independent mode.

All processors support SDDC with x4 DRAMs in independent mode.
Lockstep mode: This is also known as RAS mode. Each pair of channels shares a Write Push Logic unit to
enable lockstep. The memory controller handles all cache lines across two interfaces on an IMC. The DRAM
controllers in the same IMC share a common address decode and DMA engines for the mode. The same
address is used on both channels, such that an address error on any channel is detectable by bad ECC.

All processors support SDDC with x4 or x8 DRAMs in lockstep mode.
For Lockstep Channel Mode and Mirroring Mode, processor channels are paired together as a “Domain”.

CPU1 Mirroring/Lockstep Domain 1 = Channel A + Channel B

CPU1 Mirroring/Lockstep Domain 2 = Channel C + Channel D

CPU2 Mirroring/Lockstep Domain 1 = Channel E + Channel F

CPU2 Mirroring/Lockstep Domain 2 = Channel G + Channel H
The schedulers within each channel of a domain will operate in lockstep, they will issue requests in the same
order and time and both schedulers will respond to an error in either one of the channels in a domain.
Lockstep refers to splitting cache lines across channels. The same address is used on both channels, such
that an address error on any channel is detectable by bad ECC. The ECC code used by the memory controller
can correct 1/18th of the data in a code word. For x8 DRAMs, since there are 9 x8 DRAMs on a DIMM, a code
word must be split across 2 DIMMs to allow the ECC to correct all the bits corrupted by a x8 DRAM failure.
For RAS modes that require matching populations, the same slot positions across channels must hold the
same DIMM type with regards to number of ranks, number of banks, number of rows, and number of
columns. DIMM timings do not have to match but timings will be set to support all DIMMs populated (that is,
DIMMs with slower timings will force faster DIMMs to the slower common timing modes).
4.3 Memory RASM Features
DRAM Single Device Data Correction (SDDC): SDDC provides error checking and correction that protects
against a single x4 DRAM device failure (hard-errors) as well as multibit faults in any portion of a single DRAM
device on a DIMM (require lockstep mode for x8 DRAM device based DIMM).
Memory Disable and Map out for FRB: Allows memory initialization and booting to OS even when a memory
fault occurs.
Data Scrambling with Command and Address: Scrambles the data with address and command in "write
cycle" and unscrambles the data in "read cycle". This feature addresses reliability by improving signal
integrity at the physical layer, and by assisting with detection of an address bit error.