Penguin Computing Relion 1900e, Technical Manual

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Relion 1900e/2900e Manual
Revision 1.0 30
Potential Error Cases:

Invalid DIMM (type, organization, speed, size) – If a DIMM is found that is not a type supported by
the system, the following error will be generated: POST Error Code 8501 “DIMM Population Error”,
and a “Population Error- Fatal Error Halt 0xED”.

Invalid DIMM Installation – The DIMMs are installed incorrectly on a channel, not following the “Fill
Farthest First” rule (Slot 1 must be filled before Slot 2, Slot 2 before Slot 3). This will result in a POST
Error Code 8501 “DIMM Population Error” with the channel being disabled, and all DIMMs on the
channel will be disabled with a POST Error Code 854x “DIMM Disabled” for each. This could also
result in a “No usable memory installed” Fatal Error Halt 0xE8.

Invalid DIMM Population – A QR LRDIMM in Direct Map mode which is installed in Slot3 on a 3 DIMM
per channel server board is not allowed. This will result in a POST Error Code 8501 “DIMM
Population Error” and a “Population Error” Fatal Error Halt 0xED.

Mixed DIMM Types – A mixture of RDIMMs and/or LRDIMMs is not allowed. A mixture of LRDIMMs
operating in Direct Map mode and Rank Multiplication mode is also not allowed. This will result in a
POST Error Code 8501 “DIMM Population Error” and “Population Error” Fatal Error Halt 0xED.

Mixed DIMM Parameters – Within an RDIMM or LRDIMM configuration, mixtures of valid DIMM
technologies, sizes, speeds, latencies, etc., although not supported, will be initialized and operated on
a best effort basis, if possible.

No usable memory installed – If no enabled and available memory remains in the system, this will
result in a Fatal Error Halt 0xE8.
4.8.3 Channel Training
The Integrated Memory Controller registers are programmed at the controller level and the memory channel
level. Using the DIMM operational parameters, read from the SPD of the DIMMs on the channel, each channel
is trained for optimal data transfer between the integrated memory controller (IMC) and the DIMMs installed
on the given channel.
Potential Error Cases:

Channel Training Error – If the Data/Data Strobe timing on the channel cannot be set correctly so that
the DIMMs can become operational, this results in a momentary Error Display 0xEA, and the channel
is disabled. All DIMMs on the channel are marked as disabled, with POST Error Code 854x “DIMM
Disabled” for each. If there are no populated channels which can be trained correctly, this becomes a
Fatal Error Halt 0xEA.
4.8.3.1 Thermal (CLTT) and power throttling
Potential Error Cases:
• CLTT Structure Error – The CLTT initialization fails due to an error in the data structure passed in by
the BIOS. This results in a Fatal Error Halt 0xEF . See chapter 7 for information describing CLTT.
4.8.3.2 Built-In Self Test (BIST)
Once the memory is functional, a memory test is executed. This is a hardware-based Built In Self Test (BIST)
which confirms minimum acceptable functionality. Any DIMMs which fail are disabled and removed from the
configuration.
Potential Error Cases:
•
Memory Test Error – The DIMM has failed BIST and is disabled. POST Error Codes 852x “Failed
test/initialization” and 854x “DIMM Disabled” will be generated for each DIMM that fails. Any DIMMs