Relion 1900e/2900e Manual
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Revision 1.3
# of
DIMMs
Processor Socket 1 = Populated
Processor Socket 2 = Populated
M
A
1
A
2
A
3
B
1
B
2
B
3
C
1
C
2
C
3
D
1
D
2
D
3
E
1
E
2
E
3
F
1
F
2
F
3
G
1
G
2
G
3
H
1
H
2
H
3
16
X X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Y
16
X X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
N
24
X X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Y
M – Indicates whether the configuration supports the Mirrored Channel Mode of operation.
4.6.1
Memory Interleaving Support
The Intel® Xeon® Processor E5-4600/2600/2400/1600 v3, v4 a Product Families support multiple levels of
memory interleaving. Memory interleaving is an optimization technique which tries to locate successive data
across different memory channels, to allow for overlapping memory access.
The processors and BIOS support inter-socket interleaving across 1, 2, or 4 processor sockets, channel
interleaving across 1, 2, 3, or 4 memory channels per processor, and rank interleaving in 1, 2, 4, and 8 way
arrangements.
The BIOS will choose an interleave scheme based on the processor population and the DIMM population. If
the NUMA option is enabled, then all interleaving is strictly intra-socket to allow for locality to be controlled
by the OS. The actual locality is described in ACPI Tables.
4.6.2
NUMA Configuration Support
This BIOS includes support for Non-Uniform Memory Access (NUMA) when more than one processor is
installed in a board or one Cluster-on-Die (COD) capable processor installed.
When NUMA support is enabled, interleaving is intra socket only, and the SRAT and SLIT ACPI tables are
provided that show the locality of systems resources, especially memory, which allows a “NUMA Aware” OS
to optimize which processor threads are used by processes which can benefit by having the best access to
those resources.
NUMA support and COD support are enabled/disabled (enabled by default) by an option on the Memory RAS
and Performance screen in BIOS setup.
4.7
System Memory Sizing and Publishing
The address space configured in a system depends on the amount of actual physical memory installed, on
the RAS configuration, and on the PCIe* configuration. RAS configurations reduce the memory space
available in return for the RAS features. PCIe* devices which require address space for Memory Mapped IO
(MMIO) with 32-bit or 64- bit addressing, increase the address space in use, and introduce discontinuities in
the correspondence between physical memory and memory addresses.
The discontinuities in addressing physical memory revolve around the 4GB 32-bit addressing limit. Since the
system reserves memory address space just below the 4GB limit, and 32-bit MMIO is allocated just below
that, the addresses assigned to physical memory go up to the bottom of the PCI allocations, then “jump” to
above the 4GB limit into 64-bit space. See the comments below about Memory reservations.
4.7.1
Effects of Memory Configuration on Memory Sizing
The system BIOS supports 4 memory configurations – Independent Channel Mode and 3 different RAS
Modes. In some modes, memory reserved for RAS functions reduce the amount of memory available.
Summary of Contents for Relion 1900e
Page 2: ...Relion 1900e 2900e Manual Revision 1 3 April 2016 Intel Server Boards and Systems...
Page 11: ...Relion 1900e 2900e Manual x Revision 1 3 Figure 36 Relion 1900e 149 Figure 37 Relion 2900e 152...
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