Penguin Computing Relion 1900e, Technical Manual

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Relion 1900e/2900e Manual
21 Revision 1.3
4. System Memory
This chapter describes the architecture that drives the memory sub-system, supported memory types,
memory population rules, and supported memory RAS features.
4.1 Memory Sub-system Architecture
Figure 9. Memory Sub-system Block Diagram
Note: This generation server board has support for DDR4 DIMMs only. DDR3 DIMMs and other memory
technologies are not supported on this generation server board.
Each installed processor includes two integrated memory controllers (IMC) capable of supporting two
memory channels each. Each memory channel is capable of supporting up to three DIMMs. The processor
IMC supports the following:

Registered DIMMs (RDIMMs), and Load Reduced DIMMs (LRDIMMs) are supported

DIMMs of different types may not be mixed – this is a Fatal Error in memory initialization

DIMMs composed of 4 Gb or 8 Gb Dynamic Random Access Memory (DRAM) technology

DIMMs using x4 or x8 DRAM technology

DIMMs organized as Single Rank (SR), Dual Rank (DR), or Quad Rank (QR)

DIMM sizes of 4 GB, 8 GB, 16 GB, or 32 GB depending on ranks and technology

DIMM speeds of 1333, 1600, 1866, or 2133 MT/s (MegaTransfers/second)

Only Error Correction Code (ECC) enabled RDIMMs or LRDIMMs are supported

Only RDIMMs and LRDIMMs with integrated Thermal Sensor On Die (TSOD) are supported

Memory RASM Support:
o
DRAM Single Device Data Correction (SDDCx4)
o
Memory Disable and Map out for FRB
o
Data scrambling with command and address
o
DDR4 Command/Address parity check and retry
o
Intra-socket memory mirroring
o
Memory demand and patrol scrubbing
o
HA and IMC corrupt data containment
o
Rank level memory sparing
o
Multi-rank level memory sparing
o
Failed DIMM isolation
Intel
®
Xeon
®
E5-2600 v3, v4
Product Family
CPU-1
DDR4 – CH0
DDR4 – CH1
DDR4 – CH2
DDR4 – CH3
Intel
®
Xeon
®
E5-2600 v3,v4
Product Family
QPI 9.6
QPI 9.6
CPU-2
CH0 – DDR4
CH1 – DDR4
CH2 – DDR4
CH3 – DDR4