Penguin Computing Relion 1900e, Technical Manual, Page: 35 / 174

Relion 1900e/2900e Manual
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Enhanced Intel SpeedStep Technology builds upon that architecture using design strategies that include the
following:

Separation between Voltage and Frequency changes. By stepping voltage up and down in small
increments separately from frequency changes, the processor is able to reduce periods of system
unavailability (which occur during frequency change). Thus, the system is able to transition between
voltage and frequency states more often, providing improved power/performance balance.

Clock Partitioning and Recovery. The bus clock continues running during state transition, even when
the core clock and Phase-Locked Loop are stopped, which allows logic to remain active. The core
clock is also able to restart more quickly under Enhanced Intel SpeedStep Technology.
3.5.2.9 Intel ® Advanced Vector Extensions 2 (Intel ® AVX2)
Intel
®
Advanced Vector Extensions 2.0 (Intel
®
AVX2) is the latest expansion of the Intel instruction set. Intel®
AVX2 extends the Intel® Advanced Vector Extensions (Intel® AVX) with 256-bit integer instructions, floating-
point fused multiply add (FMA) instructions and gather operations. The 256-bit integer vectors benefit math,
codec, image and digital signal processing software. FMA improves performance in face detection,
professional imaging, and high performance computing. Gather operations increase vectorization
opportunities for many applications. In addition to the vector extensions, this generation of Intel processors
adds new bit manipulation instructions useful in compression, encryption, and general purpose software.
3.5.2.10 Intel ®
Node Manager 3.0
Intel ® Node Manager 3.0 enables the PTAS-CUPS (Power Thermal Aware Scheduling - Compute Usage Per
Second) feature of the Intel Server Platform Services 3.0 Intel ME FW. This is a grouping of separate platform
functionalities that provide Power, Thermal, and Utilization data that together offer an accurate, real time
characterization of server workload. These functionalities include the following:

Computation of Volumetric Airflow

New synthesized Outlet Temperature sensor

CPU, memory, and I/O utilization data (CUPS).
This PTAS-CUPS data can then be used in conjunction with the Intel ® Server Platform Services 3.0 Intel ® Node
Manager power monitoring/controls and a remote management application (such as the Intel ® Data Center
Manager [Intel
®
DCM]) to create a dynamic, automated, closed-loop data center management and monitoring
system.
3.5.2.11 Intel ® Secure Key
The Intel
®
64 and IA-32 Architectures instruction RDRAND and its underlying Digital Random Number
Generator (DRNG) hardware implementation is useful for providing large entropy random numbers for which
high quality keys for cryptographic protocols are created.
3.5.2.12 Intel ® OS Guard
Protects a supported operating system (OS) from applications that have been tampered with or hacked by
preventing an attack from being executed from application memory. Intel OS Guard also protects the OS
from malware by blocking application access to critical OS vectors.
3.5.2.13 Trusted Platform Module (TPM)
Trusted Platform Module is bound to the platform and connected to the PCH via the LPC bus or SPI bus. The
TPM provides the hardware-based mechanism to store or ‘seal’ keys and other data to the platform. It also
provides the hardware mechanism to report platform attestations