Paradyne 3166 DSU, User Manual

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Configuration Options
C-4
3166-A2-GB20-20 March 1999
Table C-1. Port Configuration Options (3 of 5)
Tx Clock: Int
Next Int Ext Prev
Data Port Transmit Clock. Specifies whether the transmitted data for the port is clocked
using an internal clock provided by the DSU/CSU (synchronized to the clock source
specified by the clock source configuration option in the General configuration option
group) or an external clock provided by the DTE connected to the port. When an
external clock is used, it must be synchronized to the same clock source as the
DSU/CSU.
Int – Indicates the clock is provided internally by the DSU/CSU on the TXC interchange
circuit DB (CCITT 114).
Ext – Indicates the clock is provided externally by the DTE on the XTXC interchange
circuit DA (CCITT 113). Use this selection when the clock source is set to this data port.
InvertTxC: Disab
Next Enab Disab Prev
Invert Transmit Clock. Specifies whether the clock supplied by the DSU/CSU on the
TXC interchange circuit DB (CCITT 114) is phase inverted with respect to the
Transmitted Data interchange circuit BA (CCITT 103). This configuration option is useful
when long cable lengths between the DSU/CSU and the DTE are causing data errors.
Enab – Indicates TXC supplied by the DSU/CSU on this port is phase inverted.
Disab – Indicates TXC supplied by the DSU/CSU on this port is not phase inverted.
InvrtData: Disab
Next Enab Disab Prev
Invert Transmitted and Received Data. Specifies whether the port’s transmitted data
and received data are logically inverted before being transmitted or received. This
configuration option is useful for applications where HDLC data is being transported.
Inverting the data ensures that the density requirements for the network interface are
met.
Enab – Indicates the transmitted data and received data for this port are inverted.
Disab – Indicates the transmitted data and received data for this port are not inverted.
EDL: Disab
Next Enab Disab Prev
Embedded Data Link. Specifies whether Embedded Data Link (EDL) is enabled for
Port1. If EDL is enabled, then 8 kbps of the total bandwidth allocated for this port is not
available to the synchronous data port. For example, if the port rate is 256 kbps (4 DS0
channels allocated) and EDL is enabled, then only 248 kbps is available to the port.
EDL provides the following: detection of frame synchronization, CRC of the data stream
(excluding the 8 kbps EDL), and an in-band data link (4 kbps) between the local and
remote units. The 4 kbps in-band data link can be used for performance report
messages and as an IP link for SNMP or Telnet sessions.
Enab – Indicates the port’s EDL is enabled.
Disab – Indicates the port’s EDL is disabled.
NOTES: – If the local DSU/CSU’s EDL is enabled, then the remote DSU/CSU’s
EDL must also be enabled.
– EDL is not recommended for networks in which data is examined for
routing purposes (e.g., frame relay, X.25).