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Panasonic MN103001G/F01K, User Manual

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Bus Controller (BC)

8-70

8.15 Bus Arbitration

In this microcontroller, bus arbitration is implemented through the bus authority request signal (BR) and the bus
authority release signal (BG).

If an external device asserts the BR signal, then once the current bus access that is being executed is completed, the
BG signal is asserted and the bus authority is released to the external device.  Once the BR signal is negated, this

LSI negates the BG signal in order to re-acquire the bus authority.  However, if a refresh request is generated by the
DRAM control circuit within this microcontroller while the bus authority has been released to an external device,

this LSI negates the BG signal and requests the bus authority back form the external device.  The external device
then negates the BR signal in response, and the refresh is executed.

Note that bus arbitration is performed in synchronization with SYSCLK.
Fig. 8-15-1 to 3 show the timing for releasing the bus authority to an external device, and Fig. 8-15-4 shows the

timing when a refresh request is generated while the bus authority has been released.  An, CSn, RE, WEn, RASn,
and CAS (and, if there is output on other pins related to the BC, those signals as well) are always output by this

microcontroller which has the bus authority (BG = “H”)*

1

, and go to “Hi-Z” (high impedance) when the bus

authority is released (BG = “L”).

Note that the execution of internal I/O space access requests and external memory space access requests by the
CPU while the bus authority is being released are delayed until the bus authority release is completed.

Accesses which can be executed while the bus authority is being released and accesses which are delayed until bus
authority release is completed are listed below.

(1) Accesses which can be executed while the bus authority is being released

- Internal data RAM space accesses by the CPU
- Internal ROM/internal flash memory space accesses by the CPU

(2) Accesses which are delayed until bus authority release is completed

- Internal I/O space accesses by the CPU

- External memory space accesses by the CPU

Note: For details on pins related to the BC and their statuses, refer to Table 8-5-2, “Operating Status of Pins

Concerning BC.”

*1) However, if a bus access is executed immediately before the bus authority is released to an external device, the

An signal, etc., may go to high impedance, even if BG = “H”, depending on the timing of the completion of that
bus access.  Specifically, the An and other signals are placed in the high impedance state at the following

timing relative to the timing at which the BG signal is asserted:

When 

n

fr = 4: Simultaneously, or 1, 2, or 3 MCLK cycles before

When 

n

fr = 2: Simultaneously, or 1 MCLK cycle before

Here, 

n

fr = MCLK frequency/SYSCLK frequency

Summary of Contents for MN103001G/F01K

Page 1: ...MICROCOMPUTER MN1030 MN103001G F01K LSI User s Manual Pub No 23101 050E ...

Page 2: ......

Page 3: ...3 We are not liable for any damage arising out of the use of the contents of this book or for any infringement of patents or any other rights owned by a third party 4 No part of this book may be reprinted or reproduced by any means without written permission from our company 5 This book deals with standard specification Ask for the latest individual Product Standards or Specifications in advance f...

Page 4: ......

Page 5: ...perating Mode 6 Clock Generator 7 Internal Memory 8 Bus Controller BC 9 Interrupt Controller 10 8 bit Timers 11 16 bit Timers 12 Watchdog Timer Table of Contents List of Figures and Tables 1 0 3 5 4 7 6 9 8 10 11 12 2 13 Serial Interface 13 1 General Specifications ...

Page 6: ......

Page 7: ...14 A D Converter 15 I O Ports 16 Internal Flash Memory 17 Ordering Mask ROM Appendix 14 15 16 17 ...

Page 8: ......

Page 9: ...Table of Contents List of Figures and Tables 0 ...

Page 10: ...2 4 3 Instruction Set 2 12 2 5 Interrupts 2 14 2 5 1 Overview of Interrupts 2 14 2 5 2 Registers 2 15 2 5 3 Interrupt Types 2 18 2 5 4 Interrupt Definition 2 19 3 Extension Instruction Specifications 3 1 Operation Extension Function 3 2 3 2 Extension Instructions 3 3 3 2 1 Explanation of Notations 3 3 3 2 2 Extension Block Register Set 3 4 3 2 3 Extension Instruction Details 3 5 3 2 4 Programming ...

Page 11: ... 8 5 8 6 Description of Registers 8 7 8 6 1 Memory Block 0 Control Register 8 8 8 6 2 Memory Block 1 Control Register 8 10 8 6 3 Memory Block 2 Control Register 8 14 8 6 4 Memory Block 3 Control Register 8 19 8 6 5 DRAM control register 8 22 8 6 6 Refresh count register 8 23 8 6 7 Page Row Address Register 8 24 8 6 8 Clock Control Register 8 24 8 7 Space Partitioning 8 26 8 8 Operation Clocks 8 28...

Page 12: ...6 bit Bus in Asynchronous Mode and in Address Data Multiplex Mode 8 51 8 13 10 8 bit Bus with Fixed Wait States in Synchronous Mode and in Address Data Multiplex Mode 8 52 8 13 11 8 bit Bus with Handshaking in Synchronous Mode and in Address Data Multiplex Mode 8 56 8 13 12 8 bit Bus in Asynchronous Mode and in Address Data Multiplex Mode 8 60 8 14 External Memory Space Access DRAM Space 8 62 8 14...

Page 13: ...33 11 7 1 Interval Timer and Timer Output 11 33 11 7 2 Event Counting 11 36 12 Watchdog Timer 12 1 Overview 12 2 12 2 Features 12 2 12 3 Block Diagram 12 3 12 4 Description of Registers 12 4 12 5 Description of Operation 12 7 13 Serial Interface 13 1 Overview 13 2 13 2 General purpose serial interface 13 3 13 2 1 Features 13 3 13 2 2 Block Diagram of General Purpose Serial Interface 13 5 13 2 3 De...

Page 14: ... 2 Register Descriptions 15 12 15 3 3 Pin Configuration 15 14 15 4 Port 2 15 15 15 4 1 Block Diagram 15 15 15 4 2 Register Descriptions 15 16 15 4 3 Pin Configuration 15 18 15 5 Port 3 15 19 15 5 1 Block Diagram 15 19 15 5 2 Register Descriptions 15 20 15 5 3 Pin Configurations 15 21 15 6 Port 4 15 22 15 6 1 Block Diagram 15 22 15 6 2 Register Descriptions 15 25 15 6 3 Pin Configurations 15 28 15 ...

Page 15: ...5 60 15 14 Port C 15 61 15 14 1 Block Diagram 15 61 15 14 2 Register Descriptions 15 62 15 14 3 Pin Configurations 15 63 15 15 Treatment of Unused Pins 15 64 16 Internal Flash Memory 16 1 Overview 16 2 16 2 Features 16 2 16 3 Block Diagram 16 2 16 4 Flash Memory Overwrite Mode and Settings 16 3 16 5 Flash Memory Mode 16 4 16 5 1 Description of External Pins 16 4 16 5 2 Erasure Blocks 16 7 16 6 On ...

Page 16: ...uence Flow 2 20 Fig 2 5 6 Interrupt Sequence Flow 2 21 Fig 2 5 7 Stack Frame Configuration 2 22 3 Extension Instruction Specifications Fig 3 1 1 Block Diagram of the Extension Function Unit 3 2 Fig 3 2 1 Extension Block Register Set 3 4 4 Memory Modes Fig 4 2 1 Memory Mode Pin Connection Diagram 4 3 Fig 4 3 1 Memory Space in Extension Memory Mode 4 4 Fig 4 3 2 Memory Space in Processor Mode 4 5 5 ...

Page 17: ... 8 13 10 Access Timing on a 8 bit Bus with Fixed Wait States in Synchronous Mode and in Address Data Separate Mode MCLK SYSCLK multiplied by 4 8 39 Fig 8 13 11 Access Timing on a 8 bit Bus with Fixed Wait States in Synchronous Mode and in Address Data Separate Mode MCLK SYSCLK multiplied by 2 8 40 Fig 8 13 12 Access Timing on a 8 bit Bus with Fixed Wait States in Synchronous Mode and in Address Da...

Page 18: ... MCLK SYSCLK multiplied by 2 8 58 Fig 8 13 29 Access Timing on a 8 bit Bus with Handshaking in Synchronous Mode and in Address Data Multiplex Mode MCLK SYSCLK 8 59 Fig 8 13 30 Access Timing on a 8 bit Bus in Asynchronous Mode and in Address Data Multiplex Mode MCLK SYSCLK multiplied by 4 8 61 Fig 8 14 1 DRAM Access Timing Chart 8 62 Fig 8 14 2 Case Where the RAS Precharge Interval is at Its Minimu...

Page 19: ...4 Fig 11 3 3 16 bit Timer Connection Diagram 11 5 Fig 11 3 4 Timer 10 Compare Capture Register Block Diagram 11 6 Fig 11 3 5 PWM Output Section Block Diagram 11 6 Fig 11 6 1 Compare Register Operation When Clock Source IOCLK 11 19 Fig 11 6 2 Input Capture Operation When Rising Edge is Selected 11 20 Fig 11 6 3 Pin Output Waveform 1 11 22 Fig 11 6 4 Pin Output Waveform 2 11 22 Fig 11 6 5 Pin Output...

Page 20: ... Timing Chart 8 13 17 Fig 13 2 12 Timing Chart 9 13 17 Fig 13 2 13 Timing Chart 10 13 18 Fig 13 2 14 Connections 13 19 Fig 13 2 15 Timing Chart 11 13 22 Fig 13 2 16 Timing Chart 12 13 23 Fig 13 3 1 Block Diagram 13 25 Fig 13 3 2 Connections 13 32 Fig 13 3 3 Timing Chart 13 13 33 Fig 13 3 4 Timing Chart 14 13 33 Fig 13 3 5 Timing Chart 15 13 34 Fig 13 3 6 Timing Chart 16 13 34 Fig 13 3 7 Timing Cha...

Page 21: ...ort 4 Block Diagram P45 and P43 15 22 Fig 15 6 2 Port 4 Block Diagram P44 15 23 Fig 15 6 3 Port 4 Block Diagram P42 P40 15 24 Fig 15 6 4 Port 4 Block Diagram P41 15 24 Fig 15 7 1 Port 5 Block Diagram P55 15 29 Fig 15 7 2 Port 5 Block Diagram P54 15 30 Fig 15 7 3 Port 5 Block Diagram P53 15 31 Fig 15 7 4 Port 5 Block Diagram P52 P50 15 32 Fig 15 7 5 Port 5 Block Diagram P51 15 33 Fig 15 8 1 Port 6 ...

Page 22: ...xiv 17 Ordering Mask ROM Fig 17 2 1 ROM Ordering Method 1 17 2 Fig 17 2 2 ROM Ordering Method 2 17 3 Appendix Fig C 1 Memory Connection Example Appendix 11 Fig E 1 Package Outline Appendix 14 ...

Page 23: ...erator Table 6 4 1 CKSEL Mode PLL used PLL not used 6 3 Table 6 4 2 Relationship between the Oscillation Mode and the SYSCLK MCLK and IOCLK Frequencies 6 4 Table 6 4 3 Relationship between the Input Frequency and the SYSCLK MCLK and IOCLK Frequencies When Reset is Released 6 4 8 Bus Controller BC Table 8 3 1 Characteristics of Each Bus 8 3 Table 8 5 1 External Pin Functions Relating to the Bus Con...

Page 24: ...it Rates 3 When IOCLK 8 MHz 13 15 Table 13 3 1 List of Clock Synchronous Serial Interface Registers 13 26 Table 13 4 1 List of UART Serial Interface Registers 13 38 Table 13 4 2 Bit Rates 1 When IOCLK 15 MHz 13 46 Table 13 4 3 Bit Rates 2 When IOCLK 12 MHz 13 47 Table 13 4 4 Bit Rates 3 When IOCLK 8 MHz 13 47 14 A D Converter Table 14 4 1 A D Register List 14 5 15 I O Ports Table 15 1 1 List of Re...

Page 25: ...onfiguration 15 63 Table 15 15 1Treatment of Unused Pins 15 64 16 Internal Flash Memory Table 16 4 1 Mode Settings through the External Pins 16 3 Table 16 5 1 MN1030 F01K Pin Assignments 16 5 Table 16 5 2 Pin Functions 16 6 Table 16 6 1 Flash Memory Register List 16 8 ...

Page 26: ...xviii ...

Page 27: ...1 0 1 General Specifications ...

Page 28: ... 3 3 V internal 60 MHz operation MN103001G 25 ns during 3 3 V internal 40 MHz operation MN1030F01K Power consumption TYP 300 mW during 3 3 V internal 60 MHz operation MN103001G 270 mW during 3 3 V internal 40 MHz operation MN1030F01K Compact and high performance CPU core Simple and highly efficient instruction set Number of basic instructions 46 number of extension instructions 24 number of addres...

Page 29: ...ts 38 sources _____________ External interrupts 9 sources IRQn n 7 to 0 x 8 and NMIRQ x 1 Internal interrupts 29 sources timers 18 Serial I F 8 WDT 1 A D 1 system error 1 Timers Twelve 8 bit timers all are down counters Format Reload timer Cascaded connection possible permits use as 16 to 32 bit timers Timer output possible duty ratio 1 1 12 outputs PWM output possible 8 outputs Internal clock sou...

Page 30: ...er Input ports 4 all multipurpose Output ports 15 all multipurpose Input output ports 53 all multipurpose Flash microcontroller specifications Performance identical to that of a mask ROM product guaranteed Overwriting while on board possible through serial communications Batch block erase possible Block units 8 KB multiple blocks can be selected simultaneously Package LQFP100 P 1414 1 3 Block Diag...

Page 31: ...ADM6 A6 PA5 ADM5 A5 PA4 ADM4 A4 PA3 ADM3 A3 VSS PA2 ADM2 A2 PA1 ADM1 A1 PA0 ADM0 A0 CKSEL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 AVDD VREFH P80 AN0 IRQ4 P81 AN1 IRQ5 P82 AN2 IRQ6 P83 AN3 IRQ7 AVSS EXMOD0 P90 EXMOD1 P91 VDD P92 RE P93 WE0 P94 WE1 P95 DK P96 BR VSS SYSCLK P97 VDD OSCI OSCO RST MMOD0 MMOD1 PVDD PVSS P30 BG P27 D15 P26 D14 VDD P25 D13 P24 D12 P23 D11 P22 D10...

Page 32: ...60 IRQ0 TM6IO 84 P21 D9 10 PB4 ADM12 A12 35 VSS 60 VSS 85 VSS 11 PB3 ADM11 A11 36 P96 BR 61 NMIRQ 86 VDD2 VPP 12 PB2 ADM10 A10 37 P95 DK 62 P55 SBO3 TM5IO TM13IO 87 P20 D8 13 PB1 ADM9 A9 38 P94 WE1 63 P54 SBI3 TM4IO TM12IO 88 P17 D7 14 PB0 ADM8 A8 39 P93 WE0 64 P53 SBT3 TM3IO TM11IO 89 P16 D6 15 VDD 40 P92 RE 65 P52 SBO2 TM2IO 90 P15 D5 16 PA7 ADM7 A7 41 VDD 66 P51 SBI2 TM1IO 91 P14 D4 17 PA6 ADM6...

Page 33: ...LL GND Address bus A23 to 0 O 24 Address lines 23 to 0 multipurpose A23 also serves as CS3 Data bus D15 to 0 I O 16 Data lines 15 to 0 multipurpose Address ADM15 to 0 I O 16 Address Data lines 15 to 0 A15 to 0 multipurpose Data bus Bus control MMOD1 to 0 I 2 Mode setting signals signals EXMOD1 to 0 I 2 Extension mode setting multipurpose RE O 1 Memory read signal multipurpose CS3 to 0 O 4 Chip sel...

Page 34: ...of VREFH to 0 V only AVDD 1 Analog system power supply 3 3 V AVSS 1 Analog system GND I O ports P02 to P00 O 3 Port 0 output port multipurpose P17 to P10 I O 8 Port 1 input output port multipurpose P27 to P20 I O 8 Port 2 input output port multipurpose P30 I O 1 Port 3 input output port multipurpose P45 to P40 I O 6 Port 4 input output port multipurpose P55 to P50 I O 6 Port 5 input output port mu...

Page 35: ...2 CPU 2 ...

Page 36: ...ignment 1 byte to 2 bytes basic part 0 byte to 6 bytes extension Basic performance Maximum internal operating frequency 60 MHz 1 external oscillation 15 MHz 40 MHz 2 external oscillation 10 MHz Minimum instruction execution cycle 1 cycle 16 7 ns 1 25 ns 2 Register register operations 1 cycle Load store 1 cycle Conditional branch 1 cycle to 3 cycles Pipeline 5 stage Instruction fetch decode execute...

Page 37: ...ss AU LU Barrel shifter AU Program counter block Instruction address Instruction execution control block Instruction decoder Operand data Instruction User extension function unit Internal peripheral function Bus contol block External interface Extension interface Address register Data register D0 D1 D2 D3 SP MDR PSW A0 A1 A2 A3 Internal instruction ROM Internal flash memory Internal data RAM ...

Page 38: ...isters that are used for pointers and a stack pointer This arrangement contributes greatly to the improved performance of the internal architecture through reduction of instruction code size improved parallelism in pipeline processing etc This register enables programming in C and other high level languages The loop instruction register LIR and the loop address register LAR are used to provide hig...

Page 39: ...nteger the data is sign extended from 16 bits to 32 bits with the EXTH instruction Address Register 32 bit x 4 This register is used as an address pointer and only instructions addition subtraction and comparison for address calculation are supported The address register data is used for pointers and data is normally sent to and from the memory with a 32 bit length Stack Pointer 32 bit x 1 This po...

Page 40: ...IM bits are set to the priority level of that interrupt Until the processing of the accepted interrupt is completed the CPU does not accept interrupts with the same interrupt level or lower The interrupt mask level is set to level 0 000 by a reset IE Interrupt Enable Setting this bit to 1 allows interrupts to be accepted Once the CPU accepts an interrupt request the IE bit is cleared to 0 and furt...

Page 41: ...of Control Registers Address Name Symbol Number of bits Initial value Access size x 20000000 Interrupt vector register 0 IVAR0 16 x XXXX 16 x 20000004 Interrupt vector register 1 IVAR1 16 x XXXX 16 x 20000008 Interrupt vector register 2 IVAR2 16 x XXXX 16 x 2000000C Interrupt vector register 3 IVAR3 16 x XXXX 16 x 20000010 Interrupt vector register 4 IVAR4 16 x XXXX 16 x 20000014 Interrupt vector ...

Page 42: ...R W R W R W R W R W R W R W R W R W Bit No Bit name Description 15 to 0 IVARn15 to 0 Lower 16 bits of the start address of the level interrupt handler The IVARn register should be accessed by halfwords 16 bits Byte and word access is not supported Note that the upper 16 bits of the start address of the level interrupt handler are fixed to x 4000 Core s Internal Memory Control Register MEMCTRC The ...

Page 43: ...sfer request 5 OSCID Always returns 0 when read Always write 0 15 to 6 reserved The various operating modes can be set by setting the bits as shown in the table below Oscillation control and operating mode control Operating mode STOP HALT SLEEP OSC1 OSC0 Clock CPU operation Peripheral function oscillation clock operation clock NORMAL 0 0 0 0 0 Oscillating Running Running HALT 0 1 0 0 0 Oscillating...

Page 44: ... is zero extended abs32 2 4 Instructions 2 4 1 Addressing Modes The 32 bit microcontroller is equipped with the following 6 addressing modes which are frequently used with compilers All 6 addressing modes of register direct immediate value register indirect register indirect with displacement absolute and register indirect with index can be used with data transfer group instructions The 2 addressi...

Page 45: ...ore the address of the byte data on the MSB side of halfword data is the LSB side byte data address 1 and the address of the byte data on the MSB side of word data is the LSB side byte data address 3 The bit number for bit data starts at 0 on the LSB and increases towards the MSB 1 Bit data 2 Byte data Unsigned 8 bit Signed 8 bit sign bit MSB 3 Halfword data Unsigned 16 bit Signed 16 bit sign bit ...

Page 46: ...ry Transfer of immediate values to registers MOVBU Transfer of byte data between registers and the memory zero extension MOVHU Transfer of halfword data between registers and the memory zero extension EXT 64 bit sign extension of word data EXTB 32 bit sign extension of byte data EXTBU 32 bit zero extension of byte data EXTH 32 bit sign extension of halfword data EXTHU 32 bit zero extension of half...

Page 47: ... instructions UDF User extension instruction sign extension UDFU User extension instruction zero extension Note Interrupts are prohibited and the bus is locked occupied by the CPU when executing BSET or BCLR however if a BSET or BCLR instruction is executed during program execution in external memory a bus authority release due to an external bus request may be interposed between the data read and...

Page 48: ...Priority ranking Level interrupt n n 0 to 6 Fig 2 5 1 shows an overview of the interrupt system This microcontroller is equipped with 19 interrupt group control blocks outside the CPU and controls the interrupts of each group separately Each interrupt group control block can accept up to 4 interrupt requests This allows the controller to support to 38 interrupt factors providing it with high expan...

Page 49: ...able interrupt levels Table 2 5 1 Relationship between Mask Levels and Interrupt Levels that Can Be Accepted Interrupt mask level IM2 IM1 IM0 Acceptable interrupt level 0 0 0 Interrupt prohibited only non maskable interrupts accepted 0 0 1 0 0 1 0 0 1 0 1 1 0 2 1 0 0 0 3 1 0 1 0 4 1 1 0 0 5 1 1 1 0 6 Interrupt Control Registers GnICR R W halfword byte access Interrupt control registers GnICR n 0 2...

Page 50: ...respond to each interrupt factor max 4 in the interrupt group Interrupts are enabled when the corresponding IE3 to IE0 bit is 1 Interrupt occurs when IR3 to IR0 and IE3 to IE0 are set All bits are cleared to 0 when the system is reset IR3 to IR0 Interrupt Request R W This field has up to 4 bits which register interrupt requests The IR3 to IR0 bits correspond to each interrupt After the interrupts ...

Page 51: ...r and writing cannot be performed When there are no interrupt factors of the applicable interrupt level IAGR becomes 0 Accessing IAGR is meaningless during non maskable interrupts Fig 2 5 3 Interrupt Accept Group Register Interrupt Vector Address Register IVARn R W halfword access The interrupt vector register IVAR0 to IVAR6 contains the lower 16 bits of the start address of the interrupt handler ...

Page 52: ...sing cancels the interrupt factor and then returns to the normal program using the RTI instruction External pin non maskable interrupt External pin non maskable interrupt is generated when the NMIRQ pin goes to L level If an external pin non maskable interrupt is generated the external non maskable interrupt request flag NMIF in the non maskable interrupt control register NMICR is set to 1 Watchdo...

Page 53: ...pt factor and then returns to the normal program using the RTI instruction 2 5 4 Interrupt Definition When this microcontroller accepts an interrupt first the sequences automatically processed by the hardware are executed Then control transfers to interrupt handler by the software and the interrupt handler is started up The interrupt processing sequences are described below Interrupt processing se...

Page 54: ...ler for each factor Note that because this microcontroller uses a store buffer when writing data via the bus controller it is necessary when releasing the interrupt factor to read the appropriate register immediately after clearing the interrupt factor in order to wait for the factor in the GnICR to be cleared completely Example of post processing by the interrupt handler 5 The registers are resto...

Page 55: ... occur nesting of level interrupts and non maskable interrupts is prohibited until the interrupt handler is finished by execution of the RTI instruction Interrupt Acceptance Timing If an interrupt request occurs part way through the execution of an instruction even instructions which require multiple execution cycles such as multiply divide and other instructions are aborted if possible and the in...

Page 56: ...oss the 32 bit boundary is prohibited the SP value must constantly be set to a multiple of 4 Accordingly a stack frame is allocated as shown in Fig 2 5 7 so that the SP value is constantly set to a multiple of 4 Ultimately an 8 byte area with a total of 6 bytes of information is saved Fig 2 5 7 Stack Frame Configuration SP Before the interrupt PSW PC Return address SP After the interrupt Smaller a...

Page 57: ...3 Extension Instruction Specifications 3 ...

Page 58: ...a to the extension function unit is assigned to instructions UDF20 to UDF35 Extension operations which require three or more inputs can be realized by transferring the input data to the extension function unit beforehand using instructions UDF20 to UDF35 and then performing the operation using instructions UDF00 to UDF15 The block diagram showing extension function unit connected to the CPU for th...

Page 59: ...displacement abs16 16 bit absolute abs32 32 bit absolute MDR Multiply Divide Register core built in MDRQ High speed multiplication register inside Extension Function Unit LIR Loop Instruction Register LAR Loop Address Register PSW Processor Status Word PC Program Counter Indirect addressing See 2 4 1 Addressing Modes for a detailed description regs Multiple register operand 0x Hexadecimal notation...

Page 60: ... of the 64 bit multiplication result Multiply and accumulate register higher 32 bits x 1 register This register is provided for multiply and accumulate operation instructions A multiply and accumulate operation instruction uses this register to store the high order 32 bits of the 64 bit multiply and accumulate operation result Multiply and accumulate register lower 32 bits x 1 register This regist...

Page 61: ...truction for high speed multiplication Load Instruction Format Macro Name PUTX Dm Assembler Mnemonic udf20 Dm Dm Operation The contents of Dm are transferred to the high speed multiply register MDRQ Flag Changes Flag Change Condition V C N Z Programming Cautions When udf20 Dm Dn is operated Dn is ignored ...

Page 62: ...ssembler Mnemonic udf21 Dm Dn Operation This instruction transfers the contents of Dm to the multiply and accumulate register MCRH This instruction also transfers the contents of Dn to the multiply and accumulate register MCRL The contents of the V flag are set in the multiply and accumulate overflow detect register MCVF Flag Changes Flag Change Condition V C N Z ...

Page 63: ...hen MSB of the transfer results is 1 0 in all other cases Z 1 when the transfer results are 0 0 in all other cases Programming Cautions There is a one instruction delay in the updating of the PSW to reflect flag changes However the Bcc and Lcc instructions can evaluate the flags without waiting for the flag changes to be reflected in the PSW When udf15 Dm Dn is operated Dm is ignored The operation...

Page 64: ...0 Indicates that the multiply and accumulate operation is valid C 0 Always 0 N Undefined Z Undefined When multiply and accumulate operation overflow was detected MCVF 1 Flag Change Condition V 1 Indicates that the multiply and accumulate operation is invalid C 0 Always 0 N Undefined Z Undefined Programming Cautions There is a one instruction delay in the updating of the PSW to reflect flag changes...

Page 65: ... 0 Indicates that the multiply and accumulate operation is valid C 0 Always 0 N Undefined Z Undefined When multiply and accumulate operation overflow was detected MCVF 1 Flag Change Condition V 1 Indicates that the multiply and accumulate operation is invalid C 0 Always 0 N Undefined Z Undefined Programming Cautions There is a one instruction delay in the updating of the PSW to reflect flag change...

Page 66: ... Assembler Mnemonic udf22 D0 D0 Operation This instruction clears the contents of the multiply and accumulate registers MCRH and MCRL This instruction also clears the contents of the multiply and accumulate overflow detect register MCVF Flag Changes Flag Change Condition V C N Z Programming Cautions When udf22 Dm Dn is operated Dm and Dn are ignored ...

Page 67: ...s into Dn The significant value range of the multiplicand stored in Dm before the operation is judged starting point LSB judgment unit 2 bytes and the operation is only performed for the range containing these significant values In other words the smaller the absolute value of the contents stored in Dm the quicker operation results can be obtained Flag Changes Flag Change Condition V Undefined C U...

Page 68: ...written into the high speed multiply register MDRQ and the lower 32 bits into Dn The significant value range of the multiplicand stored in imm before the operation is judged starting point LSB judgment unit 2 bytes and the operation is only performed for the range containing these significant values In other words if the number of imm bits is 16 or less the operation results will be derived faster...

Page 69: ...he lower 32 bits into Dn The significant value range of the multiplicand stored in Dm before the operation is judged starting point LSB judgment unit 2 bytes and the operation is only performed for the range containing these significant values In other words the smaller the contents stored in Dm the quicker operation results can be obtained Flag Changes Flag Change Condition V Undefined C Undefine...

Page 70: ...are written into the high speed multiply register MDRQ and the lower 32 bits into Dn The significant value range of the multiplicand stored in imm before the operation is judged starting point LSB judgment unit 2 bytes and the operation is only performed for the range containing these significant values In other words if the number of imm bits is 16 or less the operation results will be derived fa...

Page 71: ...tion to the cumulative sum 64 bits of the upper 32 bits and lower 32 bits stored in the respective multiply and accumulate registers MCRH and MCRL and it then stores the upper 32 bits of the result 64 bits in the multiply and accumulate register MCRH and the lower 32 bits in the multiply and accumulate register MCRL If an overflow from the 64 bit cumulative sum data is generated when the product i...

Page 72: ...ultiplication to the cumulative sum 64 bits of the upper 32 bits and lower 32 bits stored in the respective multiply and accumulate registers MCRH and MCRL and it then stores the upper 32 bits of the result 64 bits in the multiply and accumulate register MCRH and the lower 32 bits in the multiply and accumulate register MCRL If an overflow from the 64 bit cumulative sum data is generated when the ...

Page 73: ...signed 8 bit integer multiplier adds the resulting product to the 32 bit cumulative sum that is stored in the multiply and accumulate register MCRL and then stores the new resulting 32 bit cumulative sum back in multiply and accumulate register MCRL If an overflow from the 32 bit cumulative sum data is generated when the product is added to the cumulative sum multiply and accumulate overflow detec...

Page 74: ...lication to the cumulative sum 64 bits of the upper 32 bits and lower 32 bits stored in the respective multiply and accumulate registers MCRH and MCRL and it then stores the upper 32 bits of the result 64 bits in the multiply and accumulate register MCRH and the lower 32 bits in the multiply and accumulate register MCRL If an overflow from the 64 bit cumulative sum data is generated when the produ...

Page 75: ...is multiplication to the cumulative sum 64 bits of the upper 32 bits and lower 32 bits stored in the respective multiply and accumulate registers MCRH and MCRL and it then stores the upper 32 bits of the result 64 bits in the multiply and accumulate register MCRH and the lower 32 bits in the multiply and accumulate register MCRL If an overflow from the 64 bit cumulative sum data is generated when ...

Page 76: ...n unsigned 8 bit integer multiplier adds the resulting product to the 32 bit cumulative sum that is stored in the multiply and accumulate register MCRL and then stores the new resulting 32 bit cumulative sum back in multiply and accumulate register MCRL If an overflow from the 32 bit cumulative sum data is generated when the product is added to the cumulative sum multiply and accumulate overflow d...

Page 77: ...maximum negative value 0xffff8000 is stored in Dn In all other cases the contents of Dm are written into Dn Flag Changes Flag Change Condition V Undefined C Undefined N 1 when MSB of the operation results is 1 0 in all other cases Z 1 when the operation results are 0 0 in all other cases Programming Cautions PSW updating by flag changes is delayed by one instruction However Bcc and Lcc instruction...

Page 78: ...ximum negative value 0xff800000 is written into Dn In all other cases the contents of Dm are written into Dn Flag Changes Flag Change Condition V Undefined C Undefined N 1 when MSB of the operation results is 1 0 in all other cases Z 1 when the operation results are 0 0 in all other cases Programming Cautions PSW updating by flag changes is delayed by one instruction However Bcc and Lcc instructio...

Page 79: ...CRL are stored in Dn 2 When the value of Dm or imm8 is 16 0x00000010 When the 64 bit result of the multiply and accumulate operation that is stored in the multiply and accumulate registers MCRH and MCRL is equal to or greater than the maximum positive value for a 16 bit signed numeric value 0x0000000000007fff the maximum positive value 0x00007fff is stored in Dn If the value stored in the multiply...

Page 80: ...detected MCVF 1 Flag Change Condition V 1 Indicates that the multiply and accumulate operation is invalid C 0 Always 0 N Undefined Z Undefined Programming Cautions There is a one instruction delay in the updating of the PSW to reflect flag changes However the Bcc and Lcc instructions can evaluate the flags without waiting for the flag changes to be reflected in the PSW The operations of udf02 imm1...

Page 81: ...in Dn This instruction sets the contents of the multiply and accumulate operation overflow detect register MCVF in the V flag Flag Changes When multiply and accumulate operation overflow was not detected MCVF 0 Flag Change Condition V 0 Indicates that the multiply and accumulate operation is valid C 0 Always 0 N Undefined Z Undefined When multiply and accumulate operation overflow was detected MCV...

Page 82: ... In all other cases the contents of MCRH and MCRL are output and bits 47 through bits 16 of that output are stored in Dn This instruction sets the contents of the multiply and accumulate operation overflow detect register MCVF in the V flag Flag Changes When multiply and accumulate operation overflow was not detected MCVF 0 Flag Change Condition V 0 Indicates that the multiply and accumulate opera...

Page 83: ...that the bit number becomes smaller If search is performed up to the bit position of bit 0 without finding a 1 the C flag is set Dn is set to 0x00000000 and instruction execution ends When instruction execution starts the upper 27 bits of Dn are ignored Flag Changes When search was successful 1 was found Flag Change Condition V Undefined C 0 This indicates that search was successful N Undefined Z ...

Page 84: ...m and then swaps the positions of the high order and low order 16 bit half words and then stores the result in Dn As a result bits 31 through 24 of Dm are stored in bits 7 through 0 in Dn bits 23 through 16 of Dm are stored in bits 15 through 8 in Dn bits 15 through 8 of Dm are stored in bits 23 through 16 in Dn and bits 7 through 0 of Dm are stored in bits 31 through 24 in Dn The sample of execut...

Page 85: ...d Programming Cautions PSW updating by flag changes is delayed by one instruction However Bcc and Lcc instructions can evaluate flags without waiting for flag reflection to PSW The operations of udf08 imm8 Dn udf08 imm16 Dn and udf08 imm32 Dn are not assured In addition a system error interrupt does not occur in these cases ...

Page 86: ...gh 8 of Dm with bits 7 through 0 and bits 31 through 24 with bits 23 through 16 and then stores the result in Dn The sample of execution Before execution 0x12345678 After execution 0x34127856 Flag Changes Flag Change Condition V Undefined C Undefined N Undefined Z Undefined Programming Cautions PSW updating by flag changes is delayed by one instruction However Bcc and Lcc instructions can evaluate...

Page 87: ...t least two NOP instructions immediately before the instructions 1 The category Word half word data multiply and accumulate instruction applies to the following instructions MAC instruction MACH instruction MACU instruction MACHU instruction 2 The category byte data multiply and accumulate instruction applies to the following instructions MACB instruction MACBU instruction 3 The category multiply ...

Page 88: ...e instruction has been output As a result one cycle must be inserted between the word half word data multiply and accumulate instruction and the subsequent multiply and accumulate instruction This note applies to the following instructions Word half word data multiply and accumulate instructions MAC instruction MACH instruction MACU instruction MACHU instruction Multiply and accumulate instruction...

Page 89: ...and accumulate instruction has been output As a result two cycles must be inserted between the word half word data multiply and accumulate instruction and the subsequent MCRH MCRL access instruction This note applies to the following instructions Word half word data multiply and accumulate instructions MAC instruction MACH instruction MACU instruction MACHU instruction MCRH MCRL access instruction...

Page 90: ...data multiply and accumulate instruction has been output As a result one cycle must be inserted between the byte data multiply and accumulate instruction and the subsequent MCRH MCRL access instruction This note applies to the following instructions Byte data multiply and accumulate instructions MACB instruction MACBU instruction MCRH MCRL access instructions PUTCX instruction CLRMAC instruction G...

Page 91: ...re encountered in the case of the instruction combinations listed in the table or when the value of the multiply and accumulate operation overflow detect register MCVF is not used Preceding instruction Following instruction MAC or MACH MAC or MACH MACU or MACHU MACU or MACHU MACB MACB MACBU MACBU This note applies to the following instructions except in the case of the instruction combinations lis...

Page 92: ...tion instructions and the other extension instructions There is an error occasion CPU hung up when error actualizing condition occurs after generating error making potential condition Error making potential condition and Error actualizing condition are described in details below An interrupt on this note is defined as one of level interrupts or non maskable interrupts When ICE is used there is err...

Page 93: ...ply and accumulate instruction The case where the number of returned register by RET instruction is 0 1 or 2 is excluded And also the case where the High speed multiplication instruction uses 32 bit immediate value is excluded The interrupt occurrence Case 5 Instruction flow Branch RETF instruction with stack area outside internal RAM area High speed multiplication instruction or Multiply and accu...

Page 94: ...32 bit immediate value is excluded The interrupt occurrence Case 10 Instruction flow Branch A level interrupt with stack area outside internal RAM area High speed multiplication instruction or Multiply and accumulate instruction Interrupt program The non maskable interrupt occurrence Case 11 Instruction flow A level interrupt with stack area outside internal RAM area An 1 cycle executing instructi...

Page 95: ...instructions Memory access instructions Ones of the following instructions which access to a memory MOV instruction MOVBU instruction MOVHU instruction MOVM instruction BSET instruction BCLR instruction MOVH instruction Only store or MOVB instruction Only store Multiply and accumulate instructions MAC instruction MACH instruction MACU instruction MACHU instruction MACB instruction MACBU instructio...

Page 96: ...Extension Instruction Specifications 3 40 ...

Page 97: ...4 Memory Modes 3 4 ...

Page 98: ...he internal memory space and in the external memory space Data can be located in all address spaces and can be referenced by the MOV instruction Accordingly all addressing modes can be used to access data enabling efficient programming The address space differs according to the two memory modes of memory extension mode and processor mode For details on the address space in each memory mode refer t...

Page 99: ... Internal Flash Memory Fig 4 2 1 Memory Mode Pin Connection Diagram Note that the memory mode pins MMOD0 1 also serve as serial interface pins for debugging and for onboard writing of flash memory in the MN1030F01K The memory mode pins MMOD0 and 1 are normally input pins but when they are connected to the serial interface for debugging and for onboard writing of flash memory in the MN1030F01K they...

Page 100: ...s and control registers addresses x 40000000 to x 7FFFFFFF are the internal instruction space which contains instructions and table data and addresses x 80000000 to x BFFFFFFF are the external memory space up to 1 GB The MN103001G has 128 Kbytes of internal instruction ROM located at x 40000000 to x 4001FFFF The MN103001G also has 8 Kbytes of internal data RAM located at x 00000000 to x 00001FFF T...

Page 101: ...es x 20000000 to x 3FFFFFFF are the internal I O space up to 512 MB which is assigned to the I O ports and control registers and addresses x 40000000 to x BFFFFFFF are the external memory space up to 2 GB This microcontroller has 8 Kbytes of data RAM located at x 00000000 to x 00001FFF Note that it is prohibited to access unmounted space of the internal data space and the internal I O space When a...

Page 102: ...Memory Modes 4 6 ...

Page 103: ...5 Operating Mode 5 ...

Page 104: ...Diagram Notes All modes are entered to normal operating mode by resetting the system Changing the mode by program is performed by setting the CPUM register Interrupt Stop mode CPU and peripheral stopped Sleep mode CPU stopped peripheral operating Halt mode CPU and peripheral stopped Both the CPU and peripheral circuits operating Both the CPU and peripheral circuits stopped CPU stopped but peripher...

Page 105: ...abilization wait time tOSCW for oscillation frequency fOSC MHz is tOSCW 2n fOSC x 103 ms n 18 when CKSEL pin H or 19 when CKSEL pin L In other words when CKSEL pin H and fOSC 15 MHz tOSCW 17 476 ms Table 5 2 1 shows the status of the internal registers immediately after a reset Table 5 2 1 Status of Internal Registers Immediately after a Reset PC x 40000000 D3 to D0 Undefined SP Undefined A3 to A0...

Page 106: ...ating In SLEEP mode the microcontroller changes to normal operation mode NORMAL when an interrupt occurs Operation of various peripheral functions in the low power consumption modes The operation of the peripheral functions in SLEEP HALT and STOP mode is shown in the table below In SLEEP mode all peripheral functions operate except for the bus controller and the watchdog timer In HALT and STOP mod...

Page 107: ...6 Clock Generator 6 13 ...

Page 108: ...ited oscillators in the microcontroller When PLL is being used a clock that is a programmable multiple of the input frequency is supplied as the CPU clock MCLK A clock that is 1 4 of MCLK is supplied as the peripheral clock IOCLK A clock that is 1x the input frequency is output as the external device supply clock SYSCLK When PLL is not being used a clock that is 1 2 of the input frequency is suppl...

Page 109: ...al devices SYSCLK has the same frequency as the input frequency When external input pin CKSEL is L the frequency of the CPU core internal RAM bus controller operation clock MCLK is 1 2x the input frequency and the frequency of the internal peripheral function operation clock IOCLK is 1 8x the input frequency Note that the clock that is supplied to external devices SYSCLK 1 2x the input frequency N...

Page 110: ... 32 fc 60 1 8 fio 15 8 fosci 18 H Used MCK 1 0 01 1 8 fsys 18 2 16 fc 36 1 2 4 fio 9 MCK 1 0 00 1 8 fc 18 1 4 2 fio 4 5 8 fosci 20 L Not used Not used 1 2 4 fsys 10 1 2 4 fc 10 1 8 1 fio 2 5 In the case of the MN1030F01K the maximum frequency for MCLK is 40 MHz Table 6 4 3 Relationship between the Input Frequency and the SYSCLK MCLK and IOCLK Frequencies When Reset Is Released Oscillation mode Clo...

Page 111: ...7 Internal Memory 7 ...

Page 112: ...w Internal instruction ROM MN103001G Capacity 128 Kbytes Instruction bus width 64 bits Access cycles Instruction read 2 MCLK cycles Data read 3 MCLK cycles Internal flash memory MN1030F01K Capacity 256 Kbytes Instruction bus width 64 bits Access cycles Instruction read 2 MCLK cycles Data read 3 MCLK cycles Internal data RAM MN103001G MN1030F01K Capacity 8 Kbytes Data bus width 32 bits Access cycle...

Page 113: ...architecture in memory extension mode Fig 7 3 1 shows a block diagram of the internal memory in memory extension mode Fig 7 3 1 Internal Memory Block Diagram In Memory Extension Mode Note In processor mode internal instruction ROM and internal flash memory is not connected to the CPU core and addresses x 40000000 to x BFFFFFFF are used for external memory CPU core Internal data RAM x 00000000 x 00...

Page 114: ...Internal Memory 7 4 ...

Page 115: ...8 Bus Controller BC 8 ...

Page 116: ...block The bus width can be set to 8 or 16 bits for blocks 0 to 3 Blocks 0 to 3 can be switched between synchronous mode and asynchronous mode Blocks 0 to 3 permit the read write timing to be set through the software Blocks 1 and 2 can be used as DRAM space Blocks 2 and 3 permit use for handshaking DRAM interface Address multiplexing function Permit the read write timing to be set through the softw...

Page 117: ... data RAM 32 MCLK 1 BC bus CPU BC 32 MCLK 1 I O bus BC internal I O 32 IOCLK 1 synchronous mode EX bus BC external memory 8 16 2 SYSCLK 1 synchronous mode external bus MCLK 1 asynchronous mode 1 For a description of the operation clock refer to section 8 8 Operation Clock 2 Set by the external input pin or control register 8 4 Block Diagram Fig 8 4 1 shows the block diagram for the bus controller ...

Page 118: ...s bus I O data bus BC internal data bus BC bus interface signals I O bus interface signals MEMCTRn DRAMCTR REFCNT External interface signals EX bus external bus 23 to 0 15 to 0 data input aligner data output aligner address controller address data BC controller Buffer Store BC bus I F I O bus I F EX bus I F ...

Page 119: ...ultiplexed output when DRAM is connected D15 to 0 Input output 16 Memory data input output RAS 2 to 1 Output 2 DRAM RAS signals CAS Output 1 DRAM CAS signal for 2WE WE1 to 0 DCAS1 to 0 Output 2 DRAM CAS signals for 2 CAS DWE Output 1 DRAM WE signal for 2 CAS CS3 to 0 Output 4 Chip select signals RE Output 1 Memory read signal WE1 to 0 Output 2 Memory write signals output in byte units DK Input 1 D...

Page 120: ...AS Operate H H Hi Z DCAS1 to 0 Operate H H Hi Z DWE Operate H H Hi Z CS3 to 0 Operate H H Hi Z RE Operate H H Hi Z WE1 to 0 Operate H H Hi Z BG Operate H H L AS Operate L L Hi Z RWSEL Operate L L Hi Z Hi Z High impedance Maintain Maintains the status from the previous bus cycle L L level output H H level output Note Because the pins listed in the table at right are all multipurpose check the statu...

Page 121: ...B50 8 16 x 32000024 Memory control register 2B MEMCTR2B 16 x EB50 8 16 x 32000026 Memory control register 3B MEMCTR3B 16 x EB50 8 16 x 32000030 Memory control register 0A MEMCTR0A 16 x EFFC 8 16 x 32000032 Memory control register 1A MEMCTR1A 16 x EFFC 8 16 x 32000034 Memory control register 2A MEMCTR2A 16 x EFFC 8 16 x 32000036 Memory control register 3A MEMCTR3A 16 x EFFC 8 16 x 32000040 DRAM con...

Page 122: ... R W R W R W R W R W R W Note For the external memory access timing charts refer to section 8 13 External Memory Space Access Non DRAM Spaces Bit No Bit name Description Setting conditions 1 to 0 BCS1 to 0 Bus cycle start timing 00 0MCLK When nfr 2 settings other than 00 or 01 are prohibited 01 1MCLK When nfr 1 settings other than 00 are prohibited 10 2MCLK 11 3MCLK 3 to 2 EA1 to 0 RE WE assert ti...

Page 123: ...rt timing 00 0MCLK 11 3MCLK 10 to 8 ASN2 to 0 AS negate timing 000 prohibited Set so that 001 1MCLK ASN ASA 111 7MCLK 15 to 11 WEN4 to 0 WE negate timing Settings other than those shown below are prohibited Set so that 00011 3MCLK WEN EA 11111 31MCLK After the reset is released block 0 is set as follows Synchronous mode Address output end timing 3MCLK RE negate timing 29MCLK WE negate timing 29MCL...

Page 124: ...ming charts refer to section 8 13 External Memory Space Access Non DRAM Spaces For the timing charts when using DRAM refer to section 8 14 External Memory Space Access DRAM Spaces When not using DRAM Memory control register 1B B1DRAM 0 Bit No Bit name Description Setting conditions 1 to 0 BCS1 to 0 Bus cycle start timing 00 0MCLK When nfr 2 settings other than 00 or 01 are prohibited 01 1MCLK When...

Page 125: ...hibited use as ASC parameter 01 1MCLK 11 3MCLK 5 to 4 ADE1 to 0 Column address output timing 00 prohibited use as CAO parameter 01 1MCLK Set so that CAO ADE ASR BCS 11 3MCLK 8 to 6 BCE2 to 0 RAS hold time 000 prohibited use as RSH parameter 001 1MCLK 111 7MCLK 15 to 11 REN4 to 0 CAS pulse width 00000 prohibited use as CAS parameter 00001 1MCLK 11111 31MCLK Note When performing ICE trace emulation ...

Page 126: ...When not using DRAM Memory control register 1B B1DRAM 0 Bit No Bit name Description Setting conditions 0 DRAM Block 1 DRAM 0 Do not use as DRAM space space setting 2 BM Block 1 bus mode 0 Synchronous mode SYSCLK synchronization 1 Asynchronous mode MCLK synchronization 3 PE Block 1 software page Not using mode enable 4 BW Block 1 bus width 0 8 bits 1 16 bits 7 to 6 ASA1 to 0 AS assert timing 00 0MC...

Page 127: ...ng other than 01 is prohibited 10 to 8 ASN2 to 0 RAS precharge cycle 000 prohibited use as RP parameter 001 1MCLK 111 7MCLK 15 to 11 WEN4 to 0 WE negate timing Settings other than those shown below are prohibited Set so that 00100 4MCLK CAO ADE CAS REN WEN 11111 31MCLK After the reset is released block 1 is set as follows Address output end timing 3MCLK RE negate timing 29MCLK WE negate timing 29M...

Page 128: ...g charts refer to section 8 13 External Memory Space Access Non DRAM Spaces For the timing charts when using DRAM refer to section 8 14 External Memory Space Access DRAM Spaces When using fixed wait mode and not using DRAM Memory control register 2B B2DRAM 0 B2WM 0 Bit No Bit name Description Setting conditions 1 to 0 BCS1 to 0 Bus cycle start timing 00 0MCLK When nfr 2 settings other than 00 or 0...

Page 129: ... 31MCLK When using DRAM Memory control register 2B B2DRAM 1 B2WM 0 Bit No Bit name Description Setting conditions 1 to 0 BCS1 to 0 Row address setup timing 00 prohibited use as ASR parameter 01 1MCLK 11 3MCLK 3 to 2 EA1 to 0 Column address setup timing 00 prohibited use as ASC parameter 01 1MCLK 11 3MCLK 5 to 4 ADE1 to 0 Column address output timing 00 prohibited use as CAO parameter 01 1MCLK Set ...

Page 130: ...AS assert timing 00 0MCLK 11 3MCLK 10 to 8 ASN2 to 0 AS negate timing 000 prohibited Set so that 001 1MCLK ASN ASA 111 7MCLK 15 to 11 WEN4 to 0 WE negate timing Settings other than those shown below are prohibited Set so that 00011 3MCLK WEN EA 11111 31MCLK Memory control register 2B Register symbol MEMCTR2B Address x 32000024 Purpose Sets the bus mode access timing etc for external memory space b...

Page 131: ...LK 111 7MCLK 15 to 11 WEN4 to 0 WE negate timing Settings other than those shown below are prohibited Set so that 00100 4MCLK CAO ADE CAS REN WEN 11111 31MCLK When using handshaking mode Memory control register 2B B2DRAM 0 B2WM 1 Bit No Bit name Description Setting conditions 0 DRAM Block 2 DRAM 0 Do not use as DRAM space space setting 1 WM Block 2 wait mode 1 Handshaking mode 2 BM Block 2 bus mod...

Page 132: ...ws Address output end timing 3MCLK RE negate timing 29MCLK WE negate timing 29MCLK RE WE assert timing 3MCLK Bus cycle start timing 0MCLK Bus cycle end timing 31MCLK AS assert timing 1MCLK AS negate timing 3MCLK The bus width is 16 bits and synchronous fixed wait mode is set ...

Page 133: ... W Note For the external memory access timing charts refer to section 8 13 External Memory Space Access Non DRAM Spaces When using fixed wait mode Memory control register 3B B3WM 0 Bit No Bit name Description Setting conditions 1 to 0 BCS1 to 0 Bus cycle start timing 00 0MCLK When nfr 2 settings other than 00 or 01 are prohibited 01 1MCLK When nfr 1 settings other than 00 are prohibited 10 2MCLK 1...

Page 134: ... 3B B3WM 0 Bit No Bit name Description Setting conditions 1 WM Block 3 wait mode 0 fixed wait mode 2 BM Block 3 bus mode 0 Synchronous mode SYSCLK synchronization 1 Asynchronous mode MCLK synchronization 4 BW Block 3 bus width 0 8 bits 1 16 bits 7 to 6 ASA1 to 0 AS assert timing 00 0MCLK 11 3MCLK 10 to 8 ASN2 to 0 AS negate timing 000 prohibited Set so that 001 1MCLK ASN ASA 111 7MCLK 15 to 11 WEN...

Page 135: ...ibited Set so that 001 1MCLK ASN ASA 111 7MCLK 15 to 11 WEN4 to 0 WE negate timing 00000 0MCLK 11111 31MCLK Note Handshaking mode can only be set when MCLK frequency SYSCLK frequency 4 If MCLK frequency SYSCLK frequency 1 or 2 set B3WM 0 in MEMCTR3B After the reset is released block 3 is set as follows Address output end timing 3MCLK RE negate timing 29MCLK WE negate timing 29MCLK RE WE assert tim...

Page 136: ...l 0 2 WE control 1 2 CAS control 7 to 6 SIZE1 to 0 DRAM size 00 Shift the address 9 bits to the low order side and use as the row address 01 Shift the address 10 bits to the low order side and use as the row address 10 Shift the address 11 bits to the low order side and use as the row address 11 Shift the address 8 bits to the low order side and use as the row address 11 to 8 RERS3 to 0 Number of ...

Page 137: ...EFC REFC REFC REFC REFC REFC REFC name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Access R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit No Bit name Description Setting conditions 15 to 0 REFC 15 to 0 DRAM refresh interval x 0000 1 SYSCLK x FFFF 65536 SYSCLK The refresh interval is the REFCNT setting 1 multiplied by the SYSCLK cycle For the DRAM...

Page 138: ...nts of the page row address register are output as the row address Set the row address in the page row address register before initiating DRAM software page mode The row address that is set at this point should have already been subjected to the shift operation in accordance with the DRAM size 8 6 8 Clock Control Register Clock Control Register Register symbol CKCTR Address x 32004000 Purpose Sets...

Page 139: ...CKCTR 3 When interrupt processing is generated immediately after writing CKCTR and the stack pointer is pointing to the external memory space the internal clock multiplier changes for the first write access to the stack immediately after the interrupt is accepted Use either of the following methods in response to the above situations Method 1 In situations where it does not matter if the clock mul...

Page 140: ... made through the memory block 0 to 3 control registers and when DRAM is connected through the DRAM control register Table 8 7 1 Features of Each Block Block DRAM Bus Wait Mode Output signal used for Address data pins connection width block identification separate multiplex Block 0 Not 8 16 Fixed Synchronous CS0 Permitted permitted asynchronous Block 1 Permitted 8 16 Fixed Synchronous CS1 or RAS1 ...

Page 141: ...s extension for block 3 Block1 64 MB Block2 64 MB Block3 64 MB 8 MB space Address extension x 90000000 x 90800000 x 91000000 x 91800000 x 92000000 x 92800000 x 93000000 x 93800000 x 9C000000 x 9C800000 x 9D000000 x 9D800000 x 9E000000 x 9E800000 x 9F000000 x 9F800000 x 60000000 x 60800000 x 61000000 x 61800000 x 62000000 x 62800000 x 63000000 x 63800000 x 6C000000 x 6C800000 x 6D000000 x 6D800000 ...

Page 142: ...e Settings The values of external input pins MMOD1 to 0 and EXMOD1 to 0 set the external memory mode block 0 bus width and separate common mode for the address pins and data pins The various mode settings that can be made through the external pins are shown in Table 8 9 1 Table 8 9 1 Mode Settings by the BC External Pins Selection Setting Mode name Address data Block 0 bus width MMOD1 MMOD0 EXMOD1...

Page 143: ...chronous cycles 3 to 6 cycles 3 to 4 cycles 3 cycles 3 Asyn Number of EX bus Number of EX bus Number of EX bus Number of EX bus chronous cycles 3 cycles 3 cycles 3 cycles 3 1 2 Number of EX bus Number of EX bus Number of EX bus Number of EX bus Write Synchronous cycles 2 to 5 cycles 2 to 3 cycles 2 cycles 2 Asyn Number of EX bus Number of EX bus Number of EX bus Number of EX bus chronous cycles 2 ...

Page 144: ...tore operation is completed storing the address data and access size in the store buffer and is executed with no wait states Writes from the store buffer to internal I O or external memory are conducted in parallel with subsequent CPU operations However if there is a request from the CPU for an access to the internal I O or external memory before the write from the store buffer is completed execut...

Page 145: ... Space Access During a read the address and the read request signal RR are output in synchronization with the rising edge of IOCLK After MCLK 1 cycle the data strobe signals DSn are asserted and the I O side begins to drive the data on the data bus During a write the address and the write request signal WR are output in synchronization with the falling edge of IOCLK After MCLK 1 cycle the data str...

Page 146: ...equest from the CPU Table 8 13 1 lists the transactions that are supported for the external bus Table 8 13 1 External Bus Transaction Address Bus width Mode data Synchronization Asynchronization Separation 8 Fixed wait Handshaking Fixed wait 16 Fixed wait Handshaking Fixed wait Multiplex 8 Fixed wait Handshaking Fixed wait 16 Fixed wait Handshaking Fixed wait ...

Page 147: ...hat of SYSCLK multiplied by two Fig 8 13 3 is the timing chart in the case of a 16 bit bus with fixed wait states in synchronous mode in address data separate mode and with the frequency of MCLK equal to that of SYSCLK BCS indicates the timing during one SYSCLK cycle at which the access should start and is expressed in terms of the number of MCLK pulses since the rising edge of SYSCLK Note that wh...

Page 148: ...arious timing settings refer to the description of the memory control register in section 8 6 Description of Registers Fig 8 13 3 Access Timing on a 16 bit Bus with Fixed Wait States in Synchronous Mode and in Address Data Separate Mode MCLK SYSCLK For details on the various timing settings refer to the description of the memory control register in section 8 6 Description of Registers An Dn WEn RE...

Page 149: ... mode and with the frequency of MCLK equal to that of SYSCLK The DK signal connected to the microcontroller should be input so as to be asserted from point EA DW onward and is negated before the next access Note that when writing to byte 0 WE0 is asserted and the data is output on D7 to 0 and when writing to byte 1 WE1 is asserted and the data is output on D15 to 8 In addition in the case of a wor...

Page 150: ...in Synchronous Mode and in Address Data Separate Mode MCLK SYSCLK For details on the various timing settings refer to the description of the memory control register in section 8 6 Description of Registers An WEn RE CS2 MCLK SYSCLK Dn DK EA REN DW BCE Consumed internally by the BC Read EA WEN DW BCE Consumed internally by the BC Write DK detection start DK detection start Undefined An WEn RE CS2 WE...

Page 151: ... frequency of MCLK equal to that of SYSCLK multiplied by two Fig 8 13 9 is the timing chart in the case of a 16 bit bus in asynchronous mode in address data separate mode and with the frequency of MCLK equal to that of SYSCLK During a read the RE signal is asserted at EA x MCLK after the start of the bus cycle During a write the WE signal is asserted at EA x MCLK after the start of the bus cycle N...

Page 152: ...settings refer to the description of the memory control register in section 8 6 Description of Registers Fig 8 13 8 Access Timing on a 16 bit Bus in Asynchronous Mode and in Address Data Separate Mode MCLK SYSCLK multiplied by 2 For details on the various timing settings refer to the description of the memory control register in section 8 6 Description of Registers An Dn WEn RE CSn EA MCLK SYSCLK ...

Page 153: ...ng an 8 bit bus with fixed wait states in synchronous mode in address data separate mode and with the frequency of MCLK equal to that of SYSCLK multiplied by four Fig 8 13 11 is the timing chart in the case of a half word access using an 8 bit bus with fixed wait states in synchronous mode in address data separate mode and with the frequency of MCLK equal to that of SYSCLK multiplied by two Fig 8 ...

Page 154: ...he various timing settings refer to the description of the memory control register in section 8 6 Description of Registers Fig 8 13 12 Access Timing on a 8 bit Bus with Fixed Wait States in Synchronous Mode and in Address Data Separate Mode MCLK SYSCLK For details on the various timing settings refer to the description of the memory control register in section 8 6 Description of Registers An D7 0 ...

Page 155: ...dshaking can only be set in synchronous mode Fig 8 13 13 is the timing chart in the case of a half word access using an 8 bit bus with handshaking in synchronous mode in address data separate mode and with the frequency of MCLK equal to that of SYSCLK multiplied by four Fig 8 13 14 is the timing chart in the case of a half word access using an 8 bit bus with handshaking in synchronous mode in addr...

Page 156: ... in section 8 6 Description of Registers An WE0 RE CSn MCLK SYSCLK D7 0 DK A 0 0 EA REN DW DK detection start BCE Consumed internally by the BC A 0 1 H Read low order side Read high order side EA REN DW DK detection start BCE Consumed internally by the BC Undefined An WE0 RE CSn MCLK SYSCLK EA WEN D7 0 DK DW A 0 0 DK detection start BCE EA WEN DW A 0 1 DK detection start BCE H Write low order side...

Page 157: ...f Registers a Read Timing b Write Timing An WE0 RE CS2 MCLK SYSCLK D7 0 DK EA REN DW BCE H EA REN BCE A 0 0 DK detection start A 0 1 DK detection start DW Read low order side Read high order side Undefined Consumed internally by the BC Consumed internally by the BC An WE0 RE CS2 MCLK SYSCLK D7 0 DK EA WEN DW BCE H EA WEN BCE A 0 0 DK detection start A 0 1 DK detection start DW Write low order side...

Page 158: ...ion 8 6 Description of Registers An WE0 RE CS2 MCLK SYSCLK D7 0 DK EA REN DW BCE Consumed internally by the BC H EA REN BCE DW A 0 0 A 0 1 DK detection start DK detection start Read low order side Read high order side Undefined Consumed internally by the BC An WE0 RE CS2 MCLK SYSCLK D7 0 DK EA WEN DW BCE H EA WEN BCE DW A 0 0 A 0 1 DK detection start DK detection start Write low order side Write h...

Page 159: ...ddress signals CS signals etc are output asynchronously with SYSCLK but in synchronization with the internal MCLK In asynchronous mode accesses are all by fixed wait insertion Fig 8 13 16 is the timing chart in the case of a half word access using an 8 bit bus in asynchronous mode in address data separate mode Note that when writing WE0 is asserted and the data is output on D7 to 0 Fig 8 13 16 Acc...

Page 160: ...ncy of MCLK equal to that of SYSCLK multiplied by four Fig 8 13 18 is the timing chart in the case of a 16 bit bus with fixed wait states in synchronous mode in address data multiplex mode and with the frequency of MCLK equal to that of SYSCLK multiplied by two Fig 8 13 19 is the timing chart in the case of a 16 bit bus with fixed wait states in synchronous mode in address data multiplex mode and ...

Page 161: ...ress Data Multiplex Mode MCLK SYSCLK For details on the various timing settings refer to the description of the memory control register in section 8 6 Description of Registers AS CSn ASA ADE RWSEL MCLK SYSCLK BCS A23 to 16 ADM15 to 0 RE WEn EA BCE BCS BCE ASN ASA ADE ASN EA REN WEN Write Read data in addr addr addr addr data out 0 L Undefined A23 also serves as CS3 Undefined or Hi Z 0 L AS CSn ASA...

Page 162: ...ultiplex mode and with the frequency of MCLK equal to that of SYSCLK As shown in each timing chart the ADM15 to 0 pins go to Hi Z or the undefined output state while CSn is negated in address data multiplex mode When the bus authority is released the ADM15 to 0 pins are either pulled up or go to Hi Z depending on the setting of the I O port output mode register The DK signal connected to the micro...

Page 163: ... out 0 L Undefined 0 L Consumed internally by the BC DK detection start Undefined or Hi Z A23 also serves as CS3 MCLK SYSCLK AS CS2 ASA ADE RWSEL A23 to 16 ADM15 to 0 RE WEn EA ASN ASA ADE ASN EA REN Write Read DK DW BCE WEN BCE DW addr data in addr addr addr data out 0 L Undefined 0 L Consumed internally by the BC Consumed internally by the BC DK detection start DK detection start A23 also serves...

Page 164: ...o the description of the memory control register in section 8 6 Description of Registers MCLK SYSCLK AS CS2 BCE ASA RWSEL A23 to 16 ADM15 to 0 RE WEn EA ASN ASA ADE EA REN Write Read DK DW BCE WEN DW DK detection start DK detection start addr ADE ASN Consumed internally by the BC Consumed internally by the BC data in addr addr addr Undefined data out 0 L 0 L A23 also serves as CS3 Undefined or Hi ...

Page 165: ...o 0 pins are either pulled up or go to Hi Z depending on the setting of the I O port output mode register Note that when writing to byte 0 WE0 is asserted and the data is output on ADM7 to 0 and when writing to byte 1 WE1 is asserted and the data is output on ADM15 to 8 In addition in the case of a word access 32 bits the external access is performed twice with A 1 0 and A 1 1 Note For details on ...

Page 166: ...ing to each block Fig 8 13 24 is the timing chart in the case of a half word access using an 8 bit bus with fixed wait states in synchronous mode in address data multiplex mode and with the frequency of MCLK equal to that of SYSCLK multiplied by four Fig 8 13 25 is the timing chart in the case of a half word access using an 8 bit bus with fixed wait states in synchronous mode in address data multi...

Page 167: ...ers b Write Timing AS CSn H ADE BCS ASA RWSEL MCLK SYSCLK BCS A23 to 16 ADM15 to 0 RE WE0 EA BCE BCE ASN ASA ADE ASN EA REN REN Read low order side Read high order side A 0 1 A 0 0 A 0 0 A 0 1 0 L data in data in Undefined A23 also serves as CS3 Undefined or Hi Z 0 L AS CSn ASA ADE RWSEL MCLK SYSCLK BCS A23 to 16 ADM15 to 0 RE WE0 EA BCE BCS BCE ASN ASA ADE ASN EA WEN WEN H Write low order side Wr...

Page 168: ...e for the high order bits begins at the same rising edge of SYSCLK a Read Timing b Write Timing A23 to 16 RE AS CSn ADE ADM15 to 0 ASA RWSEL MCLK SYSCLK BCS WE0 H BCE BCS BCE ASN ADE ASA ASN EA REN EA REN Read low order side Read high order side data in data in A 0 0 0 L A 0 1 A 0 0 A 0 1 Undefined A23 also serves as CS3 Undefined or Hi Z 0 L A23 to 16 RE AS CSn ADE ADM15 to 0 ASA RWSEL MCLK SYSCL...

Page 169: ... Read Timing A23 to 16 RE AS CSn ADE ADM15 to 0 ASA RWSEL MCLK SYSCLK BCS 0 WE0 H BCE BCE ASN ADE ASA ASN EA WEN EA WEN Write low order side A 0 0 A 0 0 data out 0 L A 0 1 data out A 0 1 Undefined A23 also serves as CS3 Undefined or Hi Z Write high order side 0 L A23 to 16 RE AS CSn ADE ADM15 to 0 ASA RWSEL MCLK SYSCLK BCS 0 WE0 H BCE BCE ASN ADE ASA ASN EA REN EA REN Read low order side Read high...

Page 170: ...to that of SYSCLK multiplied by four Fig 8 13 28 is the timing chart in the case of a half word access using an 8 bit bus with handshaking in address data multiplex mode and with the frequency of MCLK equal to that of SYSCLK multiplied by two Fig 8 13 29 is the timing chart in the case of a half word access using an 8 bit bus with handshaking in address data multiplex mode and with the frequency o...

Page 171: ...ide Read low order side DK DW EA DK detection start EA DK detection start BCE Consumed internally by the BC BCE REN A 0 0 A 0 1 data in data in H A 0 0 A 0 1 Undefined 0 L 0 L Consumed internally by the BC DW A23 also serves as CS3 Undefined or Hi Z MCLK SYSCLK AS CSn ASA ADE RWSEL A23 to 16 ADM15 to 0 RE WE0 ASN ASA ADE ASN WEN Write high order side Write low order side DK DW EA BCE Consumed inte...

Page 172: ... Write high order side Write low order side DK DW BCE Consumed internally by the BC BCE EA WEN DW DK detection start H 0 L A 0 0 A 0 0 A 0 1 data out data out A 0 1 Undefined 0 L Consumed internally by the BC DK detection start A23 also serves as CS3 Undefined or Hi Z MCLK SYSCLK AS CS2 ASA ADE RWSEL A23 to 16 ADM15 to 0 RE WE0 ASN ASA ADE ASN EA REN Read high order side Read low order side DK DW ...

Page 173: ...gh order side Read low order side DK DW BCE BCE EA REN DW DK detection start DK detection start A 0 0 A 0 1 data in data in H A 0 0 A 0 1 Undefined Consumed internally by the BC Consumed internally by the BC A23 also serves as CS3 Undefined or Hi Z 0 L 0 L MCLK SYSCLK AS CS2 ASA ADE RWSEL A23 to 16 ADM15 to 0 RE WE0 ASN ASA ADE ASN EA WEN Write high order side Write low order side DK DW BCE Consum...

Page 174: ...d the address signals CSn signals etc are output asynchronously with SYSCLK but in synchronization with the internal MCLK In asynchronous mode accesses are all by fixed wait insertion The various parameters for external memory access are set in memory control registers 0 to 3 corresponding to each block Fig 8 13 30 is the timing chart in the case of a half word access using an 8 bit bus in asynchr...

Page 175: ...on of Registers A23 to 16 RE AS CSn ADE ADM15 to 0 ASA RWSEL MCLK SYSCLK WE0 H BCE BCE ASN ADE ASA ASN EA REN EA REN Read low order side Read high order side data in data in A 0 0 0 L A 0 0 A 0 1 A 0 1 Undefined A23 also serves as CS3 Undefined or Hi Z 0 L A23 to 16 RE AS CSn ADE ADM15 to 0 ASA RWSEL MCLK SYSCLK WE0 H BCE BCE ASN ADE ASA ASN EA WEN EA WEN Write low order side Write high order side...

Page 176: ...common pins are used for addresses and data DRAM cannot be supported The RAS CAS signal output timing can be set through software in the DRAM control register and memory control registers 1A B and 2A B Fig 8 14 1 shows the DRAM access timing chart Note For details on the timing settings refer to section 8 6 Description of Registers MCLK ASR CAO An RASn CAS RE Dn CAS ASC Column RSH WEn ASC Column C...

Page 177: ...s set to 16 bits Because the minimum value for the RAS precharge interval is RP ASR as shown in Fig 8 14 2 set the parameters RP and ASR to values that will satisfy the DRAM requirements Note that the minimum value that can be set for both RP and ASR is 1 Fig 8 14 2 Case Where the RAS Precharge Interval is at Its Minimum Example Where RP 1 and ASR 1 ASR CAO RASn CAS ASC RSH Lower byte read or lowe...

Page 178: ...o pins DCAS1 and DCAS0 are used for byte word control Fig 8 14 3 illustrates an example of a write using 2 WE control and Fig 8 14 4 illustrates an example of a write using 2 CAS control Fig 8 14 3 Example of an 8 bit Data Write Using 2 WE Control 16 bit Bus Width Fig 8 14 4 Example of an 8 bit Data Write Using 2 CAS Control 16 bit Bus Width MCLK An Dn CAS RASn WE1 WE0 Row Column Column Row MCLK A...

Page 179: ...its 2 Word access when the bus width is set to 16 bits Fig 8 14 5 shows the page mode read timing and write timing b Write Timing Fig 8 14 5 DRAM Page Mode Read Write Timing For details on the various timing settings refer to the description of the memory control register in section 8 6 Description of Registers a Read Timing MCLK An RASn CAS RE Dn ASR CAO Row Column CAS RSH Column CAS ASC ASC MCLK...

Page 180: ...an example Fig 8 14 6 illustrates the case where the CAS precharge interval is at its shortest CAO 1 MCLK pulses are guaranteed for the row address output interval CAO is a parameter The parameter ASR for the block in question is guaranteed for the assertion of RASn The procedure for executing this mode is described below Preparation for mode initiation 1 Set the row address in the row address reg...

Page 181: ...ASC MCLK Row CAO 1 An CAS WEn Dn ASR RASn Column Column CAS ASC ASC CAS ASC CAS Column a Read Timing b Write Timing Fig 8 14 6 Software Page Mode Read Write Timing For details on the various timing settings refer to the description of the memory control register in section 8 6 Description of Registers ...

Page 182: ... in effect any access that writes a 1 to the PE bit of the memory control register that initiated the mode is prohibited RASn remains asserted and software page mode starts over again from the output of the row address 8 14 4 DRAM refresh If the REFE bit in the DRAM control register is set CAS before RAS refresh is performed at the interval set by the refresh count register Fig 8 14 7 illustrates ...

Page 183: ...section 8 6 5 DRAM Control Register Note When using blocks 1 and 2 as DRAM space simultaneously the timing ASR RP set in memory control register 1A B is used as the refresh timing for both block 1 and block 2 Refresh count value REFC 0 REFC 0 REFC REFE bit is set Refresh is executed during idle cycle Refresh is executed with highest priority Count interval Count interval Fig 8 14 7 DRAM Refresh Op...

Page 184: ...us authority BG H 1 and go to Hi Z high impedance when the bus authority is released BG L Note that the execution of internal I O space access requests and external memory space access requests by the CPU while the bus authority is being released are delayed until the bus authority release is completed Accesses which can be executed while the bus authority is being released and accesses which are ...

Page 185: ... 15 2 Bus Arbitration Timing 2 Bus Authority Release Bus Authority Acquisition nfr 2 MCLK SYSCLK Hi Z An CSn Hi Z RE Hi Z WEn Hi Z CAS Hi Z Dn Hi Z BR BG CPU External device Bus access Standby RASn Hi Z Standby MCLK SYSCLK Hi Z An CSn Hi Z RE Hi Z WEn Hi Z CAS Hi Z Dn Hi Z BR BG CPU External device Bus access RASn Hi Z ...

Page 186: ...5 4 Bus Arbitration Timing 4 Refresh Request Generated While Bus Authority Has Been Released MCLK SYSCLK Hi Z An CSn Hi Z RE Hi Z WEn Hi Z CAS Hi Z Dn Hi Z BR BG CPU Standby RASn Hi Z External device Bus access MCLK SYSCLK Hi Z Dn BR External device Refresh Standby BG Hi Z CSn Hi Z RE Hi Z WEn Hi Z CAS Hi Z RASn Hi Z An ...

Page 187: ...re when pins ADM15 to 0 are being pulled up according to the I O port output mode register setting the pull up setting for pins ADM15 to 0 should be released before entering the stop mode in order to avoid power consumption in the stop mode due to the pull up resistance Note For details on the output mode register settings refer to Chapter 15 I O Ports 5 Interrupts are prohibited and the bus is lo...

Page 188: ... the bus authority request pin BR as a general purpose input port and the bus authority release _____ pin BG as a general purpose output port for instance so that bus requests cannot be accepted during execution of a BSET or BCLR instruction ...

Page 189: ...9 Interrupt Controller 9 ...

Page 190: ...l Can be set for each interrupt group External pin interrupt conditions Positive edge negative edge H level L level Recovery from STOP HALT or SLEEP mode is possible by means of an external pin interrupt 9 3 System Diagram Fig 9 3 1 System Diagram Interrupt request to CPU Negative edge detection NMIRQ Edge level detection Edge level detection Edge level detection Edge level detection Edge level de...

Page 191: ... 8 underflow Timer 9 underflow Timer A underflow Timer B underflow Timer 10 overflow Timer 10 compare capture A Timer 10 compare capture B Timer 11 underflow Timer 12 underflow Timer 13 underflow The interrupt level can be set separately for each group However GROUP 0 and GROUP 1 are non maskable CPU core GROUP 2 3 2 1 0 GROUP 3 3 2 1 0 x 3400010C x 34000110 GROUP 4 3 2 1 0 GROUP 5 3 2 1 0 x 34000...

Page 192: ... 11 3 2 1 0 GROUP 12 3 2 1 0 GROUP 13 3 2 1 0 x 34000124 x 34000128 x 3400012C x 34000130 x 34000134 Fig 9 4 2 Block Diagram 2 Serial 0 reception Serial 0 transmission Serial 1 reception Serial 1 transmission Serial 2 reception Serial 2 transmission Serial 3 reception Serial 3 transmission External interrupt 0 External interrupt 1 External interrupt 2 ...

Page 193: ...2 1 0 GROUP 16 3 2 1 0 GROUP 17 3 2 1 0 GROUP 18 3 2 1 0 GROUP 19 3 2 1 0 x 34000138 x 3400013C x 34000140 x 34000144 x 34000148 x 3400014C External interrupt 3 External interrupt 4 External interrupt 5 External interrupt 6 External interrupt 7 A D conversion end Fig 9 4 3 Block Diagram 3 ...

Page 194: ...ol register G7ICR 16 x 0000 8 16 x 34000120 Group 8 interrupt control register G8ICR 16 x 0000 8 16 x 34000124 Group 9 interrupt control register G9ICR 16 x 0000 8 16 x 34000128 Group 10 interrupt control register G10ICR 16 x 0000 8 16 x 3400012C Group 11 interrupt control register G11ICR 16 x 0000 8 16 x 34000130 Group 12 interrupt control register G12ICR 16 x 0000 8 16 x 34000134 Group 13 interr...

Page 195: ...a is written is shown in the table below Flag status Write data Flag status after write Flag change 0 0 0 No change 0 1 0 No change 1 0 1 No change 1 1 0 Flag is cleared SYSEF Note A non maskable interrupt cannot be generated through software 2 System error interrupt request flag SYSEF This flag cannot be cleared by writing to the non maskable interrupt control register NMICR _______ This flag can...

Page 196: ...R W R W R W R W Bit No Bit name Description 3 to 0 ID3 to 0 Group n interrupt detection register This register stores the logical product of the IEn n 3 to 0 and IRn n 3 to 0 bits If an interrupt that is enabled in the IEn bits is generated the bit corresponding to the interrupt is 1 7 to 4 IR3 to 0 Group n interrupt request register This register stores interrupt requests Each bit corresponds to ...

Page 197: ...iority levels are set in the same level the interrupt from the group with the smallest group number is accepted Perform operations concerning the interrupt priority level bits LV2 to 0 and the interrupt enable bits IE3 to 0 in the group n interrupt control register GnICR while interrupts are disabled as shown below and 0xf7ff psw Clears IE in the PSW nop Insert in order to guarantee that GnICR is ...

Page 198: ...rupt detected 3 TM3ID Timer 3 underflow interrupt detection flag 0 No interrupt detected 1 Interrupt detected 4 TM0IR Timer 0 underflow interrupt request flag 0 No interrupt request 1 Interrupt request 5 TM1IR Timer 1 underflow interrupt request flag 0 No interrupt request 1 Interrupt request 6 TM2IR Timer 2 underflow interrupt request flag 0 No interrupt request 1 Interrupt request 7 TM3IR Timer ...

Page 199: ...rupt detected 3 TM7ID Timer 7 underflow interrupt detection flag 0 No interrupt detected 1 Interrupt detected 4 TM4IR Timer 4 underflow interrupt request flag 0 No interrupt request 1 Interrupt request 5 TM5IR Timer 5 underflow interrupt request flag 0 No interrupt request 1 Interrupt request 6 TM6IR Timer 6 underflow interrupt request flag 0 No interrupt request 1 Interrupt request 7 TM7IR Timer ...

Page 200: ...rupt detected 3 TMBID Timer B underflow interrupt detection flag 0 No interrupt detected 1 Interrupt detected 4 TM8IR Timer 8 underflow interrupt request flag 0 No interrupt request 1 Interrupt request 5 TM9IR Timer 9 underflow interrupt request flag 0 No interrupt request 1 Interrupt request 6 TMAIR Timer A underflow interrupt request flag 0 No interrupt request 1 Interrupt request 7 TMBIR Timer ...

Page 201: ...rrupt detection flag 0 No interrupt detected 1 Interrupt detected 3 0 is returned when this bit is read 4 T10UIR Timer 10 overflow interrupt request flag 0 No interrupt request 1 Interrupt request 5 T10AIR Timer 10 compare capture A interrupt request flag 0 No interrupt request 1 Interrupt request 6 T10BIR Timer 10 compare capture B interrupt request flag 0 No interrupt request 1 Interrupt request...

Page 202: ...interrupt detection flag 0 No interrupt detected 1 Interrupt detected 3 0 is returned when this bit is read 4 T11IR Timer 11 underflow interrupt request flag 0 No interrupt request 1 Interrupt request 5 T12IR Timer 12 underflow interrupt request flag 0 No interrupt request 1 Interrupt request 6 T13IR Timer 13 underflow interrupt request flag 0 No interrupt request 1 Interrupt request 7 0 is return...

Page 203: ...ission interrupt detection flag 0 No interrupt detected 1 Interrupt detected 3 and 2 0 is returned when these bits are read 4 SC0RIR Serial 0 reception interrupt request flag 0 No interrupt request 1 Interrupt request 5 SC0TIR Serial 0 transmission interrupt request flag 0 No interrupt request 1 Interrupt request 7 and 6 0 is returned when these bits are read 8 SC0RIE Serial 0 reception interrupt ...

Page 204: ...ission interrupt detection flag 0 No interrupt detected 1 Interrupt detected 3 and 2 0 is returned when these bits are read 4 SC1RIR Serial 1 reception interrupt request flag 0 No interrupt request 1 Interrupt request 5 SC1TIR Serial 1 transmission interrupt request flag 0 No interrupt request 1 Interrupt request 7 and 6 0 is returned when these bits are read 8 SC1RIE Serial 1 reception interrupt ...

Page 205: ...ission interrupt detection flag 0 No interrupt detected 1 Interrupt detected 3 and 2 0 is returned when these bits are read 4 SC2RIR Serial 2 reception interrupt request flag 0 No interrupt request 1 Interrupt request 5 SC2TIR Serial 2 transmission interrupt request flag 0 No interrupt request 1 Interrupt request 7 and 6 0 is returned when these bits are read 8 SC2RIE Serial 2 reception interrupt ...

Page 206: ...ission interrupt detection flag 0 No interrupt detected 1 Interrupt detected 3 and 2 0 is returned when these bits are read 4 SC3RIR Serial 3 reception interrupt request flag 0 No interrupt request 1 Interrupt request 5 SC3TIR Serial 3 transmission interrupt request flag 0 No interrupt request 1 Interrupt request 7 and 6 0 is returned when these bits are read 8 SC3RIE Serial 3 reception interrupt ...

Page 207: ...IQ0ID External interrupt 0 interrupt detection flag 0 No interrupt detected 1 Interrupt detected 3 to 1 0 is returned when these bits are read 4 IQ0IR External interrupt 0 interrupt request flag 0 No interrupt request 1 Interrupt request 7 to 5 0 is returned when these bits are read 8 IQ0IE External interrupt 0 interrupt enable flag 0 Disabled 1 Enabled 11 to 9 0 is returned when these bits are re...

Page 208: ...IQ1ID External interrupt 1 interrupt detection flag 0 No interrupt detected 1 Interrupt detected 3 to 1 0 is returned when these bits are read 4 IQ1IR External interrupt 1 interrupt request flag 0 No interrupt request 1 Interrupt request 7 to 5 0 is returned when these bits are read 8 IQ1IE External interrupt 1 interrupt enable flag 0 Disabled 1 Enabled 11 to 9 0 is returned when these bits are re...

Page 209: ...IQ2ID External interrupt 2 interrupt detection flag 0 No interrupt detected 1 Interrupt detected 3 to 1 0 is returned when these bits are read 4 IQ2IR External interrupt 2 interrupt request flag 0 No interrupt request 1 Interrupt request 7 to 5 0 is returned when these bits are read 8 IQ2IE External interrupt 2 interrupt enable flag 0 Disabled 1 Enabled 11 to 9 0 is returned when these bits are re...

Page 210: ...IQ3ID External interrupt 3 interrupt detection flag 0 No interrupt detected 1 Interrupt detected 3 to 1 0 is returned when these bits are read 4 IQ3IR External interrupt 3 interrupt request flag 0 No interrupt request 1 Interrupt request 7 to 5 0 is returned when these bits are read 8 IQ3IE External interrupt 3 interrupt enable flag 0 Disabled 1 Enabled 11 to 9 0 is returned when these bits are re...

Page 211: ...IQ4ID External interrupt 4 interrupt detection flag 0 No interrupt detected 1 Interrupt detected 3 to 1 0 is returned when these bits are read 4 IQ4IR External interrupt 4 interrupt request flag 0 No interrupt request 1 Interrupt request 7 to 5 0 is returned when these bits are read 8 IQ4IE External interrupt 4 interrupt enable flag 0 Disabled 1 Enabled 11 to 9 0 is returned when these bits are re...

Page 212: ...IQ5ID External interrupt 5 interrupt detection flag 0 No interrupt detected 1 Interrupt detected 3 to 1 0 is returned when these bits are read 4 IQ5IR External interrupt 5 interrupt request flag 0 No interrupt request 1 Interrupt request 7 to 5 0 is returned when these bits are read 8 IQ5IE External interrupt 5 interrupt enable flag 0 Disabled 1 Enabled 11 to 9 0 is returned when these bits are re...

Page 213: ...IQ6ID External interrupt 6 interrupt detection flag 0 No interrupt detected 1 Interrupt detected 3 to 1 0 is returned when these bits are read 4 IQ6IR External interrupt 6 interrupt request flag 0 No interrupt request 1 Interrupt request 7 to 5 0 is returned when these bits are read 8 IQ6IE External interrupt 6 interrupt enable flag 0 Disabled 1 Enabled 11 to 9 0 is returned when these bits are re...

Page 214: ...IQ7ID External interrupt 7 interrupt detection flag 0 No interrupt detected 1 Interrupt detected 3 to 1 0 is returned when these bits are read 4 IQ7IR External interrupt 7 interrupt request flag 0 No interrupt request 1 Interrupt request 7 to 5 0 is returned when these bits are read 8 IQ7IE External interrupt 7 interrupt enable flag 0 Disabled 1 Enabled 11 to 9 0 is returned when these bits are re...

Page 215: ... 0 ADID A D conversion end interrupt detection flag 0 No interrupt detected 1 Interrupt detected 3 to 1 0 is returned when these bits are read 4 ADIR A D conversion end interrupt request flag 0 No interrupt request 1 Interrupt request 7 to 5 0 is returned when these bits are read 8 ADIE A D conversion end interrupt enable flag 0 Disabled 1 Enabled 11 to 9 0 is returned when these bits are read 12 ...

Page 216: ...During a register read this register returns the smallest group number of the groups that are generating an interrupt of the interrupt levels indicated by IM2 to 0 the PSW Because when an interrupt generated the interrupt levels accepted by the CPU are set in IM2 to 0 this register returns a group number that is generating an interrupt level accepted by the CPU However if IM2 to 0 are changed if t...

Page 217: ...tion setting LSB 5 IR2TG1 IRQ2 pin trigger condition setting MSB 00 Positive edge 01 Negative edge 10 H level 11 L level 6 IR3TG0 IRQ3 pin trigger condition setting LSB 7 IR3TG1 IRQ3 pin trigger condition setting MSB 00 Positive edge 01 Negative edge 10 H level 11 L level 8 IR4TG0 IRQ4 pin trigger condition setting LSB 9 IR4TG1 IRQ4 pin trigger condition setting MSB 00 Positive edge 01 Negative ed...

Page 218: ...terrupt factor belongs Once the interrupt group is determined the interrupt request is sent by manipulating the interrupt control register GnICR for that group in order to notify the CPU of the interrupt group level The interrupt group number is also set in the interrupt acceptance group register IAGR The interrupt level of a group can be determined by reading the interrupt priority level register...

Page 219: ...ery in response to edge input is not possible SLEEP mode Positive edge negative edge H level L level 3 When writing a GnICR register in an interrupt program in order to clear IR and ID and then returning from the interrupt program in order to gain synchronization with the bus controller store buffer be certain to perform an I O bus access between the execution of the instruction movbu etc that is ...

Page 220: ...Interrupt Controller 9 32 ...

Page 221: ...10 8 bit Timers 9 10 ...

Page 222: ...Cascaded connection Cascaded connection can be used to form a pure 16 24 or 32 bit timer Timers 0 to 3 4 to 7 and 8 to B can be cascaded together Interrupts An interrupt request is generated when a timer underflow occurs Timers 0 to B Timer output Output of underflow cycle divided in half is possible Timers 0 to B Timers 0 and 8 1 and 9 2 and A and 3 and B share multipurpose pins PWM output PWM ou...

Page 223: ...timers Fig 10 3 1 8 bit Timer Block Diagram Timers 0 to 3 TMnBR TMnBC CK0 CK1 LDE CNE TMnMD TMnIN0 TMnIN1 TMnIN2 TMnIN3 Underflow Reload Load TMnCI TMnCLK TMnIRQ TMnOUT Cascaded signal from higher order timer Underflow interrupt Timer output TMnCO Cascaded signal Count operation enabled Reset mode register base register binary counter T R Q Timer n n 0 1 2 3 CK2 TMnIN5 TMnIN6 TMnIN7 TMnIN4 Clock o...

Page 224: ...e register buffer TMnBR TMnBC CK0 CK1 LDE CNE TMnMD TMnIN0 TMnIN1 TMnIN2 TMnIN3 TMnCI TMnCLK TMnIRQ TMnCO CK2 TMnIN5 TMnIN6 TMnIN7 TMnIN4 OM0 OM1 TMnCMP Compare register Underflow Reload Load Cascaded signal from higher order timer Underflow interrupt Timer output Cascaded signal Count operation enabled mode register base register binary counter Clock output Reload Load ...

Page 225: ...lock Timer 8 to B TM8OUT Timer 8 Timer 9 Timer A Timer B TM9OUT TMAOUT TMBOUT TM8IRQ TM9IRQ TMAIRQ TMBIRQ TM8IRQ Timer interrupt 8 TM9IRQ Timer interrupt 9 TMAIRQ Timer interrupt A TMBIRQ Timer interrupt B TM0IO TM0IN7 TM1IN7 TM2IN7 TM3IN7 TM8IN7 TM9IN7 TMAIN7 TMBIN7 TM1IO TM2IO TM3IO TMnIN1 TMnIN0 TMnIN2 TMnIN5 TMnIN4 TMnIN6 TMnIN1 TMnIN0 TMnIN2 TMnIN5 TMnIN4 TMnIN6 TM4IN7 TM5IN7 TM6IN7 TM7IN7 TM...

Page 226: ... TM1IN6 TM2IN1 TM2IN0 TM2IN3 TM2IN2 TM2CI Timer 2 TM2OUT TM2IRQ TM2CO TM2CLK TM2IN5 TM2IN4 TM2IN7 TM2IN6 TM3IN1 TM3IN0 TM3IN3 TM3IN2 TM3CI Timer 3 TM3OUT TM3IRQ TM3CO TM3CLK TM3IN5 TM3IN4 TM3IN7 TM3IN6 TM0OUT Timer output 0 TM1IRQ Timer interrupt 1 TM1OUT Timer output 1 TM2IRQ Timer interrupt 2 TM2OUT Timer output 2 TM3IRQ Timer interrupt 3 TM3OUT Timer output 3 Timers 0 to 3 block IOCLK 32 IOCLK ...

Page 227: ...6OUT TM6IRQ TM6CO TM6CLK TM6IN5 TM6IN4 TM6IN7 TM6IN6 TM7IN1 TM7IN0 TM7IN3 TM7IN2 TM7CI Timer 7 TM7OUT TM7IRQ TM7CO TM7CLK TM7IN5 TM7IN4 TM7IN7 TM7IN6 IOCLK 8 IOCLK TM4OUT Timer output 4 TM5IRQ Timer interrupt 5 TM5OUT Timer output 5 TM6IRQ Timer interrupt 6 TM6OUT Timer output 6 TM7IRQ Timer interrupt 7 TM7OUT Timer output 7 TM0IRQ TM1IRQ TM2IRQ TM4IO pin input TM5IO pin input TM6IO pin input TM7I...

Page 228: ...N4 TM9IN7 TM9IN6 TMAIN1 TMAIN0 TMAIN3 TMAIN2 TMACI Timer A TMAOUT TMAIRQ TMACO TMACLK TMAIN5 TMAIN4 TMAIN7 TMAIN6 TMBIN1 TMBIN0 TMBIN3 TMBIN2 TMBCI Timer B TMBOUT TMBIRQ TMBCO TMBCLK TMBIN5 TMBIN4 TMBIN7 TMBIN6 IOCLK 8 IOCLK TM8OUT Timer output 8 TM9IRQ Timer interrupt 9 TM9OUT Timer output 9 TMAIRQ Timer interrupt A TMAOUT Timer output A TMBIRQ Timer interrupt B TMBOUT Timer output B TM0IRQ TM1IR...

Page 229: ... output or PWM output can be selected 10 4 Functions Table 10 4 1 lists the functions of each 8 bit timer Table 10 4 1 List of 8 bit Timer Functions B A 9 8 7 6 5 4 3 2 0 1 Timer Interval timer Event counter Timer output PWM output Interrupt SIF0 2 clock source SIF1 3 clock source A D conversion start trigger Cascaded connection ...

Page 230: ...4001012 Timer 2 base register TM2BR 8 x 00 8 16 x 34001013 Timer 3 base register TM3BR 8 x 00 8 x 34001014 Timer 4 base register TM4BR 8 x 00 8 16 32 x 34001015 Timer 5 base register TM5BR 8 x 00 8 x 34001016 Timer 6 base register TM6BR 8 x 00 8 16 x 34001017 Timer 7 base register TM7BR 8 x 00 8 x 34001018 Timer 8 base register TM8BR 8 x 00 8 16 32 x 34001019 Timer 9 base register TM9BR 8 x 00 8 x...

Page 231: ... 8 x 00 8 16 x 34001037 Timer 7 compare register TM7CMP 8 x 00 8 x 34001038 Timer 8 compare register TM8CMP 8 x 00 8 16 32 x 34001039 Timer 9 compare register TM9CMP 8 x 00 8 x 3400103A Timer A compare register TMACMP 8 x 00 8 16 x 3400103B Timer B compare register TMBCMP 8 x 00 8 x 34001070 Timer ouput selection TMOSL 8 x 00 8 16 x 34001071 Prescaler control register TMPSCNT 8 x 00 8 Table 10 5 1...

Page 232: ...the timer clock source When pin input is selected the rising edge of the pin input signal is counted For details on each timer clock sources refer to Table 10 5 3 8 bit Timer Clock Sources 5 to 3 0 is returned when these bits are read 6 TMnLDE Timer n initialization flag Initializes timer n 0 Normal operation 1 Initialize Loads the value in TMnBR into TMnBC Resets timer output n to L level 7 TMnCN...

Page 233: ...timer clock sources refer to Table 10 5 3 8 bit Timer Clock Sources 3 0 is returned when this bit is read 4 TMnOM0 Timer n output mode flag LSB 5 TMnOM1 Timer n output mode flag MSB These bits select the timer n output waveform For details on each PWM output waveform refer to Table 10 5 2 PWM Output Waves 00 Underflow 1 2 cycle output L level output during timer n initialization 01 Underflow 1 2 c...

Page 234: ...nCNE is set to 0 Operation is not guaranteed if TMnCNE and TMnLDE are both set to 1 at the same time Table 10 5 2 PWM Output Waves TMnOM0 setting Upon initialization When TMnBC and TMnCMP settings match In event of an underflow 0 L level output H level output L level output 1 H level output L level output H level output ...

Page 235: ...r 5 Timer 6 Timer 7 IOCLK IOCLK Cascaded with timer 5 IOCLK Cascaded with timer 6 Cascaded with timer 4 Setting prohibited 100 101 110 111 Timer 2 underflow Timer 2 underflow Timer 0 underflow Timer 0 underflow Timer 0 underflow IOCLK 8 IOCLK 8 IOCLK 8 IOCLK 8 IOCLK 32 IOCLK 32 IOCLK 32 IOCLK 32 Timer 1 underflow Timer 1 underflow Timer 1 underflow Timer 2 underflow TM4IO pin input TM7IO pin input...

Page 236: ...ccurred TMnBC generates an underflow interrupt every value set in TMnBR 1 counts When PWM output has been selected for timers 4 to B the PWM output cycle is set Timer n binary counter n 0 1 2 3 4 5 6 7 8 9 A B Register symbol TMnBC Address x 34001020 n 0 x 34001021 n 1 x 34001022 n 2 x 34001023 n 3 x 34001024 n 4 x 34001025 n 5 x 34001026 n 6 x 34001027 n 7 x 34001028 n 8 x 34001029 n 9 x 3400102A...

Page 237: ...P6 CMP5 CMP4 CMP3 CMP2 CMP1 CMP0 Reset 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W This register sets the PWM output duty ratio The duty ratio is value set in TMnCMP value set in TMnBR 1 When data is written to this register it is written in the compare register buffer The set value is loaded from the compare register buffer into the compare register under the following conditions 1 Whe...

Page 238: ...ut signal for the TM0IO pin 0 Selects the timer 0 output 1 Selects the timer 8 output 1 TMOSL1 Timer output selection flag 1 Selects the output signal for the TM1IO pin 0 Selects the timer output 1 1 Selects the timer output 9 2 TMOSL2 Timer output selection flag 2 Selects the output signal for the TM2IO pin 0 Selects the timer output 2 1 Selects the timer output A 3 TMOSL3 Timer output selection ...

Page 239: ...TMPS name CNE Reset 0 0 0 0 0 0 0 0 Access R W R R R R R R R Bit No Bit name Description 6 to 0 0 is returned when these bits are read 7 TMPSCNE Prescaler operation enable flag Enables disables operation of the 1 8 IOCLK and 1 32 IOCLK prescaler 0 Operation disabled 1 Operation enabled The prescaler that is controlled by this register is also used with the 16 bit timers ...

Page 240: ... in TMnBR 1 x Clock source cycle 2 Select the clock source Select the clock source through TMnCK 2 0 in the TMnMD register When using either 1 8 IOCLK or 1 32 IOCLK as the clock source set TMPSCNE to 1 in the TMPSCNT register to enable prescaler operation 3 Output mode setting Applies to timers 4 to B only Set TMnOM 1 0 in the TMnMD register to underflow 1 2 cycle output and select the polarity af...

Page 241: ...e next time that an underflow is generated and then the interrupt cycle changes Procedure for ending operation 1 Stop the timer counting operation Set TMnCNE to 0 in the TMnMD register stopping the counting operation 2 Initialize the timer if necessary If TMnLDE is set to 1 in the TMnBR register the value that is set in TMnMD is loaded into TMnBC as the initial value and the timer output is reset ...

Page 242: ...al Timer Operation When Clock Source IOCLK TMnBC value TMnBR setting value TMnCNE Interrupt request Timer output x 00 x 01 TMnBR value TMnBRvalue 1 x 00 TMnBR value IOCLK Timer output TMnOUT TMnBR value 1 value in TMnBR 1 x IOCLK Interrupt request signal TMnIRQ TMnBC value ...

Page 243: ... bit Timers 10 23 Fig 10 6 3 Interval Timer Operation Using Prescaler Timer output TMnOUT x 00 x 01 TMnBR value TMnBR value 1 IOCLK TMnBC value Interrupt request signal TMnIRQ Counter clock TMnBR value 2 ...

Page 244: ... I O port register settings refer to chapter 15 I O Ports 5 Enable the timer counting operation Once TMnCNE is set to 1 in the TMnMD register the counting operation is enabled Once the counting operation is enabled the rising edge on the pin input is counted and an interrupt request is generated when there is an underflow in the binary counter Refer to Fig 10 6 4 If the value in the TMnBR register...

Page 245: ...t 6 3 or 1 5 SYSCLK cycles when MCLK frequency SYSCLK frequency 1 2 or 4 respectively Event counting is not possible when IOCLK is stopped in HALT or STOP mode Fig 10 6 4 Event Counting Operation Interrupt request signal TMnIRQ TMnBC value Count clock x 01 IOCLK Pin input TMnIO x 00 TMnBR value TMnBR value 1 ...

Page 246: ...r Lower Timer 1 Timer 0 Highest Lowest Timer 2 Timer 1 Timer 3 Timer 2 When using cascaded 8 bit timers as a 24 bit timer Highest Lowest Timer 1 Timer 0 Lowest Timer 2 Timer 3 When using cascaded 8 bit timers as a 32 bit timer Highest Timer 5 Timer 4 Timer 6 Timer 5 Timer 7 Timer 6 Timer 9 Timer 8 Timer A Timer 9 Timer B Timer A Timer 5 Timer 4 Timer 6 Timer 5 Timer 7 Timer 6 Timer 9 Timer 8 Timer...

Page 247: ...he registers for the cascaded timers When changing the values that are set in TMnBR while the counter is in operation change TMnBR for the cascaded timers simultaneously 2 Select the clock source Select any desired clock source for the lowest order timer Set the clock source for the higher timers all except for the lowest timer to cascaded connection Example 1 When using timer 0 and timer 1 as a 1...

Page 248: ... Stop the counting operation Stop the counting operation by either one of the following two methods 1 Stop the counting operation for each of the cascaded timers one at a time in order starting from the lowest timer 2 Stop the counting operation for all of the cascaded timers simultaneously 6 Timer output and interrupts Only the timer output and interrupt requests from the highest of the cascaded ...

Page 249: ...n Fig 10 6 6 IOCLK is selected as the clock source for timer 0 When TM0BC underflows the value that is set in TM0BR is loaded into TM0BC and the value in TM1BC is decremented by one When TM1BC underflows the value that is set in TM1BR is loaded into TM1BC TM0BC value Interrupt request signal TM1IRQ TM1BC value x 00 x 01 TM0BR value TM0BR value 1 IOCLK x 00 x 01 TM0BR value TM0BR value 1 x 00 x 01 ...

Page 250: ...s decremented by one If TM1BC does equal x 00 then when TM0BC underflows the values that are set in TM0BR and TM1BR are loaded into TM0BC and TM1BC respectively and a timer 1 interrupt request is generated TM0BC value Interrupt request signal TM1IRQ TM1BC value x 00 x 01 IOCLK x 00 x 01 TM0BR value TM0BR value 1 x 00 x 01 Interrupt request signal TM0IRQ x 00 x 01 TM1BR value x FE x FF x FF TM1BR v...

Page 251: ... to enable prescaler operation 4 Set the output mode timers 4 to B only Set TMnOM 1 0 in the TMnMD register to PWM output and select the polarity upon initialization 5 Initialize the timer Set TMnLDE in the TMnMD register to 1 to initialize timer n The value set in TMnBR is loaded into TMnBC as the initial value The value in the compare register buffer is loaded into the TMnCMP register PWM output...

Page 252: ...ated and the duty ratio of the PWM waveform changes Procedure for ending operation 1 Stop the timer counting operation Set TMnCNE to 0 in the TMnMD register stopping the counting operation 2 Initialize the timer if necessary If TMnLDE is set to 1 in the TMnMD register the timer is initialized The value set in TMnBR is loaded into TMnBC as the initial value The value in the compare register buffer ...

Page 253: ...MP value Fig 10 6 8 PWM Output When Clock Source IOCLK and L Level Is Output Upon Initialization Fig 10 6 9 PWM Output When Using Prescaler and H Level Is Output Upon Initialization Counter clock TMnBC value Timer output TMnOUT TMnBR value x 00 IOCLK Interrupt request signal TMnIRQ TMnBR value 1 x counter clock TMnBR value x 00 TMnCMP value x counter clock TMnCMP value ...

Page 254: ...8 bit Timers 10 34 ...

Page 255: ...11 16 bit Timers 11 ...

Page 256: ... of one shot output Two outputs Polarity of pin output can be set Input capture Each pin can be set individually to rising edge falling edge or both edges Two inputs An interrupt request is generated upon capture When both edges is set an interrupt request is generated at both the rising edge and the falling edge Interrupts An interrupt request is generated when the binary counter overflows An int...

Page 257: ...ck Diagram Timer 10 Timer 10 TM10CA TM10BC Compare capture A register Binary counter TM10CB Compare capture B register Pin input control TM10IRQ Overflow interrupt TM10AIRQ Compare capture interrupt A TM10INA TM10INB TM10IN0 TM10IN1 TM10IN2 TM10IN5 TM10IN6 TM10IN7 TM10IN4 TM10BIRQ Compare capture interrupt B TM10OUTA TM10OUTB Capture Capture Match Match Pin output control ...

Page 258: ... TMnMD Underflow Reload Load TMnIRQ TMnOUT Underflow interrupt Timer output Counting operation enable Reset Mode register Base register Binary counter T R Q CK2 TMnIN0 TMnIN1 TMnIN2 TMnIN5 TMnIN6 TMnIN7 TMnIN4 Fig 11 3 2 16 bit Timer Block Diagram Timers 11 12 and 13 ...

Page 259: ...0IN5 TM10IN7 TM10IN6 TM10IOB IOCLK 1 32 TMPSCNT Reset Prescaler control register 1 8 IOCLK prescaler Timer 0 underflow Timer 1 underflow Timer 2 underflow TM10IA TM10IB Timer 11 underflow interrupt Timer 12 underflow interrupt Timer 13 underflow interrupt Timer 10 compare capture A interrupt Timer 10 compare capture B interrupt TM10BIRQ Edge detection Edge detection Edge detection Edge detection E...

Page 260: ...Underflow R S Low order 8 bits High order 8 bits Low order 8 bits High order 8 bits TMnOUT PWM output High order 8 bits Low order 8 bits Compare capture register Compare register buffer Timer 10 compare capture registers TM10CA TM10CB Compare capture register Compare register buffer Data bus Register write Register read Double buffer mode Load timing Single buffer mode Initialization flag TM10LDE ...

Page 261: ...tput PWM output Interrupts Input capture One shot output Up down counting Timer 10 Timer 11 Timer 12 Timer 13 Underflow Underflow Underflow Overflow Compare capture A Compare capture B Variable cycle and duty ratio 1 output Fixed cycle 2 outputs 2 inputs either single edge or both edges Up counting Down counting Down counting Edge can be selected Rising edge Rising edge Rising edge 2 outputs ...

Page 262: ...TM12BR 16 x 0000 16 x 34001096 Timer 13 base register TM13BR 16 x 0000 16 x 340010A0 Timer 10 binary counter TM10BC 16 x 0000 16 x 340010A2 Timer 11 binary counter TM11BC 16 x 0000 16 x 340010A4 Timer 12 binary counter TM12BC 16 x 0000 16 x 340010A6 Timer 13 binary counter TM13BC 16 x 0000 16 x 340010B0 Timer 10 compare capture A mode register TM10MDA 8 x 00 8 16 x 340010B1 Timer 10 compare captur...

Page 263: ...is selected counting occurs at the rising edge of the pin input Note For details on the clock sources for each timer refer to Table 11 5 2 16 bit Timer Clock Sources 3 0 is returned when this bit is read 4 TM10CAE Counter clear enable flag Enables disables clearing of TM10BC when TM10BC and TM10CA match 0 Do not clear TM10BC becomes a 16 bit free running counter 1 Clear When TM10CA is set as a com...

Page 264: ...its 4 bits 11 14 bits basic wave 8 bits 6 bits 13 TM10PME Timer 10 PWM output waveform selection flag This bit selects the PWM output waveform for timer 10 0 Normal waveform 1 PWM output with additional bits The PWM waveform is output with the resolution that is set in TM10PM1 and 0 The number of bits that was set in TM10PM1 and 0 is the number of bits in TM10BC that function as a binary counter 1...

Page 265: ...Loads the value in TMnBR into TMnBC resets timer output n and loads the value in the compare register buffer into the compare register 7 TMnCNE Timer n operation enable flag Enables disables the timer n counting operation 0 Operation disabled 1 Operation enabled Note When setting TMnCNE to 1 do so while TMnLDE is set to 0 When setting TMnLDE to 1 do so while TMnCNE is set to 0 Operation is not gua...

Page 266: ...er n 10 11 12 13 Register symbol TMnBC Address x 340010A0 n 10 x 340010A2 n 11 x 340010A4 n 12 x 340010A6 n 13 Purpose This is the binary counter for timer n The counter value can be read from this register Bit No 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit TMn TMn TMn TMn TMn TMn TMn TMn TMn TMn TMn TMn TMn TMn TMn TMn name BC15 BC14 BC13 BC12 BC11 BC10 BC9 BC8 BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 Reset...

Page 267: ...y when the timer is initialized 011 Reset when TMnBC matches TMnCA 100 Toggled output Output is inverted when TMnBC matches TMnCA 101 110 111 Setting prohibited 3 0 is returned when this bit is read 4 TM10ACE Timer 10 capture A operation enable flag Enables disables capture operation for TM10CA 0 Disables capture operation Pin input is ignored 1 Enables capture operation 5 TM10AEG Timer 10 A pin p...

Page 268: ... when the timer is initialized 011 Reset when TMnBC matches TMnCB 100 Toggled output Output is inverted when TMnBC matches TMnCB 101 110 111 Setting prohibited 3 0 is returned when this bit is read 4 TM10BCE Timer 10 capture B operation enable flag Enables disables capture operation for TM10CB 0 Disables capture operation Pin input is ignored 1 Enables capture operation 5 TM10BEG Timer 10B pin pol...

Page 269: ...t as a double buffer compare register data that is written to TM10CA is stored temporarily in a buffer so it is possible that after writing TM10CA a read of TM10CA will still return the value that was previously stored there The value set in the buffer is loaded into the compare register under the conditions described below In any of these cases the value in TM10BC becomes x 0000 1 When timer 10 i...

Page 270: ...s stored temporarily in a buffer so it is possible that after writing TM10CB a read of TM10CB will still return the value that was previously stored there The value set in the buffer is loaded into the compare register under the conditions described below In any of these cases the value in TM10BC becomes x 0000 1 When timer 10 is initialized 2 When an overflow occurs while TM10CAE is set to 0 3 Wh...

Page 271: ...E Reset 0 0 0 0 0 0 0 0 Access R W R R R R R R R Bit No Bit name Description 6 to 0 0 is returned when these bits are read 7 TMPSCNE Prescaler operation enable flag Enables disables 1 8 IOCLK and 1 32 IOCLK prescaler operation 0 Prescaler operation disable 1 Prescaler operation enabled This prescaler also serves as the 1 8 IOCLK or 1 32 IOCLK prescaler that is used by 8 bit timers ...

Page 272: ... mode Set the TM10MDA register as follows TM10AO2 1 0 Don t care TM10ACE 0 Capture operation disabled TM10AEG Don t care TM10AM1 0 00 Compare register single buffer or 01 Compare register double buffer If the value in the compare register will change while the counting operation is in progress be certain to set double buffer 2 Set the comparison value in the compare capture A register Set the comp...

Page 273: ...nabled TM10AEG Don t care If single edge is selected below select either rising edge or falling edge here TM10AM1 0 10 Capture register single edge or 11 Capture register dual edge If dual edge is selected the setting in TM10AEG is ignored Once the timer 10 counting operation is enabled the value in TM10BC is captured in TM10CA and a compare capture A interrupt request is generated according to th...

Page 274: ... is in progress by setting TM10ACE to 0 When TM10CAE is set to 1 in the TM10MD register and TM10CA is set as a capture register TM10BC is cleared when the value is captured in TM10CA If TM10CB is set as a double buffer compare register the value that is set in the buffer is loaded into the compare register at this time Fig 11 6 2 Input Capture Operation When Rising Edge Is Selected IOCLK TM10CA Pi...

Page 275: ...0 in order to resume normal operation manipulating the TM10AEG or TM10BEG flags does not change the output level on the corresponding pins 2 Setting the output waveform for the counting operation If the TM10CNE flag in the TM10MD register is set to 1 thus enabling the timer 10 counting operation the waveform selected by the TM10AO0 1 and 2 flags in the TM10MDA register is output to the TM10IOA pin...

Page 276: ...11 6 3 Pin Output Waveform 1 Fig 11 6 4 shows the output waveform for the TM10IOA pin when Set when TM10BC matches TM10CA and reset when TM10BC overflows is set If the set and reset conditions occur simultaneously the reset takes precedence Fig 11 6 4 Pin Output Waveform 2 Match between TM10BC and TM10CA Match between TM10BC and TM10CB TM10CNE TM10IOA pin output when TM10AEG 0 TM10IOA pin output w...

Page 277: ...Waveform 4 Fig 11 6 7 shows the output waveform for the TM10IOA pin when Toggled output is set Fig 11 6 7 Pin Output Waveform 5 TM10CNE Match between TM10BC and TM10CA TM10IOA pin output when TM10AEG 0 TM10IOA pin output when TM10AEG 1 Don t Care Don t Care Match between TM10BC and TM10CA TM10IOA pin output when TM10AEG 0 TM10IOA pin output when TM10AEG 1 Don t Care Don t Care Match between TM10BC...

Page 278: ...ing is ignored TM10PME 0 Selects the normal waveform TM10LDE 0 Normal operation TM10CNE 0 Stops counting operation When using 1 8IOCLK or 1 32IOCLK as the clock source set TMPSCNE in the TMPSCNT register to 1 to enable prescaler operation before enabling the counting operation for timer 10 3 Initialize the timer Set TM10LDE in the TM10MD register to 1 in order to initialize timer 10 TM10BC is clea...

Page 279: ...r to 0 If TM10TGE and TM10CNE are both set to 0 simultaneously there is a possibility that TM10CNE will be set again depending on the pin input timing Therefore always be sure to set TM10TGE to 0 first and then set TM10CNE to 0 Fig 11 6 8 Timer 10 Startup by an External Trigger When Rising Edge is Selected Pin input TM10IOB Edge detection x 0001 TM10CNE x 0000 x 0003 x 0002 x 0004 TM10BC value IOC...

Page 280: ...the normal waveform TM10LDE 0 Normal operation TM10CNE 0 Stops counting operation When using 1 8 IOCLK or 1 32 IOCLK as the clock source set TMPSCNE in the TMPSCNT register to 1 to enable prescaler operation before enabling the counting operation for timer 10 4 Initialize the timer Set TM10LDE in the TM10MD register to 1 in order to initialize timer 10 TM10BC is cleared and the pin output is reset...

Page 281: ...D register to 0 If TM10TGE and TM10CNE are both set to 0 simultaneously there is a possibility that TM10CNE will be set again depending on the pin input timing Therefore always be sure to set TM10TGE to 0 first and then set TM10CNE to 0 Fig 11 6 9 One shot Operation When Clock Source IOCLK Fig 11 6 10 One shot Operation When Using Prescaler x 0000 TM10CA value TM10CA value 1 IOCLK x 0000 x 0001 TM...

Page 282: ...lock source TM10CAE 1 Clears TM10BC when TM10CA matches TM10BC TM10ONE 0 Disables one shot operation TM10TGE 0 Disables timer start by an external trigger TM10PM1 0 Don t care This setting is ignored TM10PME 0 Selects the normal waveform TM10LDE 0 Normal operation TM10CNE 0 Stops counting operation When using 1 8IOCLK or 1 32IOCLK as the clock source set TMPSCNE in the TMPSCNT register to 1 to ena...

Page 283: ...r output is reset If the TM10CA register is set as a double buffer the value in the compare register buffer is loaded into the compare register If TM10LDE is not set to 1 after the timer is stopped the binary counter the compare register and the pin output are maintained as they were before the timer was stopped If TM10CNE is set to 1 again the count resumes from the state that was in effect immed...

Page 284: ...re capture A register TM10CA Compare register A buffer Fig 11 6 13 Timer 10 Interval Timer Operation When Clock Source IOCLK Fig 11 6 14 Timer 10 Interval Timer Operation When Using Prescaler IOCLK TM10BC value Count clock x 0000 x 0001 TM10CA value TM10CA value 1 Set value 1 Set value 1 Set value 2 Set value 2 If double buffer is set the set value is loaded from the buffer at the same time that T...

Page 285: ...ion ratio in TM10CA A compare capture A interrupt request is then generated when the specified edge is counted value set in TM10CA 1 times on the TM10IOB pin 4 Set the operating mode Set the TM10MD register as described below TM10CK2 1 0 111 Sets the TM10IOB pin input as the clock source TM10CAE 1 Clears TM10BC when TM10CA matches TM10BC TM10ONE 0 Disables one shot operation TM10TGE 0 Disables tim...

Page 286: ...ze the timer if necessary If TM10LDE is set to 1 in the TM10MD register TM10BC is cleared and the timer output is reset If the TM10CA register is set as a double buffer the value in the compare register buffer is loaded into the compare register If TM10LDE is not set to 1 after the timer is stopped the binary counter the compare register and the pin output are maintained as they were before the ti...

Page 287: ... 2 Select the clock source Select the clock source through TMnCK 2 0 in the TMnMD register When using 1 8IOCLK or 1 32IOCLK as the clock source set TMPSCNE in the TMPSCNT register to 1 to enable prescaler operation before enabling the counting operation for timers 11 12 or 13 3 Initialize the timer Set TMnLDE to 1 in the TMnMD register to initialize timer n The value set in TMnBR is loaded into TM...

Page 288: ...ration 1 Stop the timer counting operation Set TMnCNE to 0 in the TMnMD register stopping the counting operation 2 Initialize the timer if necessary If TMnLDE is set to 1 in the TMnMD register the value that is set in TMnBR is loaded into TMnBC as the initial value and the timer output is reset If TMnLDE is not set to 1 after the timer is stopped the binary counter and the pin output are maintaine...

Page 289: ... Using the Prescaler x 0000 x 0001 TMnBR value TMnBR value 1 IOCLK TMnBC value Timer output TMnOUT Count clock TMnBR value 2 Interrupt request signal TMnIRQ x 0000 x 0001 TMnBR value TMnBR value 1 x 0000 TMnBR value IOCLK TMnBC value Timer output TMnOUT TMnBR value 1 TMnBR value 1 x IOCLK Interrupt request signal TMnIRQ ...

Page 290: ... counting operation The counting operation is enabled when the TMnCNE in the TMnMD register is set to 1 Once the counting operation is enabled the counter counts rising edges on the pin input When an underflow occurs in the binary counter an interrupt is generated and the value set in TMnBR is loaded into TMnBC Refer to Fig 11 7 4 If the value in the TMnBR register is changed while the counting op...

Page 291: ... or 1 5 SYSCLK cycles when MCLK frequency SYSCLK frequency 1 2 or 4 respectively Also note that event counting is not possible when IOCLK is stopped in HALT or STOP mode Fig 11 7 4 Event Count Operation x 0001 IOCLK TMnBC value Pin input TMnIO x 0000 TMnBR value TMnBR value 1 Count clock Interrupt request signal TMnIRQ ...

Page 292: ...16 bit Timers 11 38 ...

Page 293: ...12 Watchdog Timer 11 12 ...

Page 294: ...L oscillating frequency 8 MHz to 20 MHz 17 19 21 23 or 25 bits can be selected Overflow cycle 4 369 ms to 1118 481 ms when the CKSEL pin input is H and the oscillating frequency is 15 MHz A non maskable interrupt is generated when a watchdog timer overflow occurs Watchdog timer overflow output A flag can be set to 1 when a watchdog timer overflow occurs The watchdog timer overflow output can be se...

Page 295: ... 2 12 1 2 14 1 2 16 STOP mode WDBC WDCTR CKSEL L H CKSEL input H PLL is using L PLL is not using Clock source selection SYSCLK Internal reset generation Internal reset signal 1 2 8 bit binary counter 16 bit binary counter RSTCTR register CK0 Reset Reset SYSCLK 8 bit binary counter wdovf CK1 CK2 OVF OVT RST CNE 12 3 Block Diagram Fig 12 3 1 Block Diagram ...

Page 296: ...ntrol register RSTCTR 8 x 00 8 Watchdog binary counter Register symbol WDBC Address x 34004000 Purpose Reading this counter returns the counter value of the high order eight bits of the watchdog timer Bit No 7 6 5 4 3 2 1 0 Bit WD WD WD WD WD WD WD WD name BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 Reset 0 0 0 0 0 0 0 0 Access R R R R R R R R Bit No Bit name Description 7 to 0 WDBC7 to 0 Counter value of the...

Page 297: ... order 8 bits of the counter When the reset state is released the clock source corresponding to 001 below is selected When CKSEL is H When CKSEL is L 000 1 28 of the OSCI input 1 29 001 1 210 of the OSCI input 1 211 010 1 212 of the OSCI input 1 213 011 1 214 of the OSCI input 1 215 100 1 216 of the OSCI input 1 217 101 Setting prohibited 110 Setting prohibited 111 Setting prohibited Overflow cycl...

Page 298: ...taneously overwrite the WDOVT flag If this flag is overwritten the value of watchdog overflow reset is not guaranteed 2 When changing the values of WDCK2 to 0 first stop the watchdog timer and reset the counter Reset control register Register symbol RSTCTR Address x 34004004 Purpose This flag causes the program to generate an internal reset Bit No 7 6 5 4 3 2 1 0 Bit CHIP name RST Reset 0 0 0 0 0 ...

Page 299: ...ation wait time can be selected from among times that are calculated as follows Overflow cycle 2 n WDCK x 2 f x 103 ms Where n 16 CKSEL pin is H or n 17 CKSEL pin is L WDCK WDCK 2 0 f Oscillation input frequency unit MHz An oscillation stabilization wait time of at least 14 ms is recommended If the WDCNE flag is 1 a non maskable interrupt is not generated even when recovering from STOP mode Fig 12...

Page 300: ...top mode release request external pin interrupt Overflow 4 369 ms to 1118 481 ms Recommended value is 14 ms or longer when CKSEL H and the oscillating input frequency is 15 MHz Oscillation stabilization wait time SYSCLK Internal clock SYSCLK supply enabled Watchdog timer count value OSCI input ...

Page 301: ...o reset the counter When switching to HALT or SLEEP mode set the WDCNE flag to 0 to turn off the watchdog timer Self reset operation The chip resets internally when a 1 is written to the CHIPRST bit in the RSTCTR register The oscillation stabilization wait operation is not performed The reset generated by writing the CHIPRST flag is an internal reset signal within the chip and does not manifest it...

Page 302: ...Watchdog Timer 12 10 ...

Page 303: ...13 Serial Interface 13 ...

Page 304: ...Diagram Transmission interrupt 0 Reception interrupt 0 IOCLK Timer 3 underflow Timer 9 underflow Transmitter TXD TXC Receiver RXC RXD SBO0 SBT0 SBI0 General purpose serial interface Clock sync only serial interface n 2 SBO2 SBT2 SBI2 Transmitter TXD TXC Receiver RXC RXD Transmission interrupt 2 Reception interrupt 2 SBO3 SBT3 SBI3 Transmission interrupt 3 Reception interrupt 3 Transmitter Receiver...

Page 305: ...reception bit sequence LSB or MSB selectable Clock source 1 2 1 8 or 1 32 of IOCLK 1 8 of timer 3 or timer 9 underflow 1 2 of timer 9 underflow External clock Maximum bit rate 7 5 Mbit s when IOCLK is 15 MHz Error detection during reception Parity errors overrun errors Buffers Independent buffers for transmission and reception Reception and transmission buffers are both double buffers Interrupts T...

Page 306: ... when IOCLK is 15 MHz Error detection during reception Parity errors overrun errors framing errors Buffers Independent buffers for transmission and reception Reception and transmission buffers are both double buffers Interrupts Transmission interrupts Transmission end or transmission buffer empty selectable Reception interrupts Reception end or reception end with error selectable I2C mode Master t...

Page 307: ...3 underflow Send break Transfer clock Reception buffer Shift register Interrupt request generation Transmission interrupt request Reception interrupt request Timer 9 underflow Serial interface 0 Interrupt mode register SC0ICR SC0CTR Control register Status register SC0STR Transmission bit counter Reception bit counter SBI0 SBO0 Output control I O Port Block Set the serial signals in the I O port c...

Page 308: ... Address x 34000800 Purpose This register sets the serial interface 0 operation control conditions Bit No 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit SC0 SC0 SC0 SC0 SC0 SC0 SC0 SC0 SC0 SC0 SC0 SC0 SC0 SC0 SC0 SC0 name TXE RXE BKE IIC MD1 MD0 OD TOE CLN PB2 PB1 PB0 STB CK2 CK1 CK0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit No Bit ...

Page 309: ...lected 9 SC0OD Transmission and reception bit sequence selection 0 From LSB 1 From MSB 10 SC0MD0 Protocol selection LSB 11 SC0MD1 Protocol selection MSB 00 UART mode 01 Clock synchronous mode 1 the SBO0 pin is used as a data output and the SBI0 pin is used as a data input 10 I2C mode 11 Clock synchronous mode 2 the SBO0 pin is used as a data input and output and input on the SBI0 pin is ignored 12...

Page 310: ...ccurs 1 Interrupt request when a parity error occurs 3 0 is returned when this bit is read 4 SC0TI Transmission interrupt factor selection 0 Transmission end 1 Transmission buffer empty 5 Reserved Setting 1 is prohibited 6 0 is returned when this bit is read 7 SC0DMD Data output retained during external clock transmission valid only in clock synchronous mode 0 Set data pin H at end of transmission...

Page 311: ...R R R R R R R Bit No Bit name Description 0 SC0OEF Overrun error indication 0 No error 1 Overrun error occurred 1 SC0PEF Parity error indication 0 No error 1 Parity error occurred 2 SC0FEF Framing error indication 0 No error 1 Framing error occurred 3 0 is returned when this bit is read 4 SC0RBF Reception buffer status indication 0 Reception buffer empty 1 Data exists in the reception buffer 5 SC0...

Page 312: ...MD1 and 0 01 the SBO pin is always an output and the SBI pin is always an input When using SBO pin as a data input output SC0MD1 and 0 11 the SBO pin is an output only during transmission and is normally an input When SC0TOE is 0 the SBT pin is an output only during transmission with the internal clock and is normally an input Furthermore when SC0TOE is 1 the SBT pin is always an output when the i...

Page 313: ...he MSB bit 7 is ignored The SC0TXF flag is set to 1 when data is written to SC0TXB and is set to 0 at the end of transmission The SC0TBF flag is set to 1 when data is written to SC0TXB and is set to 0 at the start of transmission bp1 bp2 bp3 bp4 bp5 bp6 bp7 PTY bp0 SBO pin SBT pin Data write SC0TXF flag SC0TBF flag Interrupt request when set to transmission buffer empty Interrupt request when set ...

Page 314: ...microcomputer side In this case interrupt requests are also generated by the transmission source Receive data according to the following procedure 1 Select the internal clock as the reference clock and set the parity character length etc 2 Enable both the transmission operation and the receiving operation 3 When dummy data is written to the transmission buffer the clock is sent and reception begin...

Page 315: ...rred An overrun error is generated when reception of the next data is completed before previously received data is read from the SC0RXB In this event the previously received data is lost The overrun error indicator flag SC0OEF is updated at the moment the final data bit is received A parity error is generated when 0 fixed parity is set and a 1 is received when 1 fixed parity is set and a 0 is rece...

Page 316: ... to divide the clock signal The division ratio is determined as follows Timer division ratio INT IOCLK frequency bit rate 8 0 5 In the example described above the timer division ratio is 98 In the timer 3 base register set TM3BR 97 and set SC0CK2 to 0 100 IOCLK divided by 98 will then be supplied to the serial interface as the input clock The bit rate error is calculated as follows Bit rate error ...

Page 317: ...K 12 MHz Bit rate bit s When cascaded When using prescalers Timer division ratio Bit rate error Timer division ratio Bit rate error 19 200 78 0 16 Not using 9 600 156 0 16 Not using 4 800 313 0 16 156 x 2 0 16 2 400 625 0 0 125 x 5 0 0 1 200 1 250 0 0 125 x 10 0 0 Table 13 2 4 Bit Rates 3 When IOCLK 8 MHz Bit rate bit s When cascaded When using prescalers Timer division ratio Bit rate error Timer ...

Page 318: ...e MSB bit 7 is ignored The SC0TXF flag is set to 1 when data is written to SC0TXB and is set to 0 at the end of transmission The SC0TBF flag is set to 1 when data is written to SC0TXB and is set to 0 at the start of transmission SBO pin Data write SC0TXF flag SC0TBF flag Interrupt request when set to transmission buffer empty Interrupt request when set to transmission end bp1 bp2 bp3 bp4 bp5 bp6 b...

Page 319: ...RXB In the case of a 7 bit transfer the MSB bit 7 is 0 The SC0RXF flag is set to 1 at the start of reception when the start bit is detected and is set to 0 at the end of reception The SC0RBF flag is set to 1 at the end of reception and is set to 0 when SC0RXB is read SC0RXF flag SBI pin SC0RBF flag bp1 bp2 bp3 bp4 bp5 bp6 bp7 PTY bp0 ST SP Interrupt request Data read SBI pin bp1 bp2 bp3 bp4 bp5 bp...

Page 320: ...fore previously received data is read from the SC0RXB In this event the previously received data is lost The overrun error indicator flag SC0OEF is updated at the moment the final data bit is received A parity error is generated when 0 fixed parity is set and a 1 is received when 1 fixed parity is set and a 0 is received when even parity is set and an odd number of ones is received or when odd par...

Page 321: ...smission and slave reception SDA and SCL require pull up resistors Connect pull up resistors externally The SBO pin is an open drain input output and the SBT pin is an open drain output Fig 13 2 14 Connections SBO SBI SBT Master transmission reception SDA SCL Slave transmission reception Slave transmission reception ...

Page 322: ... desired However the clock source must be selected from among the following four 1 8 IOCLK 1 32 IOCLK 1 8 timer 3 underflow 1 8 timer 9 underflow Set the parity bits each transmission reception 3 I O port setting Set the I O ports to SBT and SBO Leave the I O port input output control registers set to input 4 Interrupt mode register setting SC0ICR register Set the interrupt sources as transmission...

Page 323: ...parity error Read the parity error indication flag SC0PEF When parity is set to 0 fixed the value of SC0PEF is the value of Ack When parity is set to 1 fixed the inverted value of SC0PEF is the value of Ack When performing consecutive transmission reception operations repeat steps 1 to 4 Wait function under SCL control The transmission reception operation waits until SCL is released if SCL is driv...

Page 324: ...nd the stop sequence is generated 3 Transmission reception disable Disable the transmission operation and the reception operation Set SC0TXE and SC0RXE to 0 Be sure to always perform this step every time after the stop sequence is sent 4 I O port setting To perform further transmission reception operations set the I O ports to SBT and SBO Fig 13 2 15 Timing Chart 11 bp7 bp6 bp5 bp4 bp3 bp2 bp1 bp0...

Page 325: ...ation and the reception operation Set SC0TXE and SC0RXE to 0 Set the I2C mode selection flag to 0 4 I O port setting Set the I O ports to SBT and SBO 5 Transmission reception enable Enable the transmission operation and the reception operation Set SC0TXE and SC0RXE to 1 6 Start sequence resend Set the I2C mode selection flag to 1 A low signal is output on the SBO pin and the start sequence is sent...

Page 326: ...er 8 underflow 1 2 of timer 8 underflow for either serial interface 1 1 8 of timer 3 or timer 9 underflow 1 2 of timer 9 underflow for either serial interface 2 External clock for either serial interface 1 or 2 Maximum bit rate 7 5 Mbit s when IOCLK is 15 MHz Error detection during reception Parity errors overrun errors Buffers Independent buffers for transmission and reception Reception and trans...

Page 327: ...fer Shift register Interrupt request generation Transmission interrupt request Reception interrupt request Serial interface n n 1 2 Timer 2 underflow when n 1 Timer 3 underflow when n 2 Timer 8 underflow when n 1 Timer 9 underflow when n 2 Transmission bit counter Reception bit counter SCnCTR Control register SCnSTR Status register SCnICR Interrupt mode register SBOn Output control I O Port Block ...

Page 328: ...f bits Initial value Access size x 34000810 Serial 1 control register SC1CTR 16 x 0000 8 16 x 34000814 Serial 1 interrupt mode register SC1ICR 8 x 00 8 x 34000818 Serial 1 transmission buffer SC1TXB 8 x 00 8 x 34000819 Serial 1 reception buffer SC1RXB 8 x 00 8 x 3400081C Serial 1 status register SC1STR 8 x 00 8 x 34000820 Serial 2 control register SC2CTR 16 x 0000 8 16 x 34000824 Serial 2 interrup...

Page 329: ...ock source selection LSB 1 SCnCK1 Clock source selection 2 SCnCK2 Clock source selection MSB 000 1 2 IOCLK 001 1 8 IOCLK 010 1 32 IOCLK 011 1 2 timer 8 underflow When n 1 1 2 timer 9 underflow When n 2 100 1 8 timer 2 underflow When n 1 1 8 timer 3 underflow When n 2 101 1 8 timer 8 underflow When n 1 1 8 timer 9 underflow When n 2 110 Setting prohibited 111 External clock 3 0 is returned when thi...

Page 330: ...BTn pin is an input when an external clock is selected 9 SCnOD Transmission and reception bit sequence selection 0 From LSB 1 From MSB 10 SCnMD0 Protocol selection 0 Clock synchronous mode 1 the SBOn pin is used as a data output and the SBIn pin is used as a data input 1 Clock synchronous mode 2 the SBOn pin is used as a data input and output and input on the SBIn pin is ignored 13 to 11 0 is retu...

Page 331: ...n 0 Reception end 1 Reception end with error 1 0 is returned when this bit is read 2 SCnRES Reception error interrupt factor selection 0 Interrupt request when an overrun or parity error occurs 1 Interrupt request when a parity error occurs 3 0 is returned when this bit is read 4 SCnTI Transmission interrupt factor selection 0 Transmission end 1 Transmission buffer empty 5 Reserved Setting 1 is pr...

Page 332: ...ess R W R W R W R W R W R W R W R W Data is transmitted by writing it to this buffer Serial n reception buffer n 1 2 Register symbol SCnRXB Address x 34000819 n 1 x 34000829 n 2 Purpose This register reads in the reception data of serial interface n Bit No 7 6 5 4 3 2 1 0 Bit SCn SCn SCn SCn SC0n SCn SCn SCn name RXB7 RXB6 RXB5 RXB4 RXB3 RXB2 RXB1 RXB0 Reset 0 0 0 0 0 0 0 0 Access R R R R R R R R ...

Page 333: ...ndication 0 No error 1 Overrun error occurred 1 SCnPEF Parity error indication 0 No error 1 Parity error occurred 3 to 2 0 is returned when these bits are read 4 SCnRBF Reception buffer status indication 0 Reception buffer empty 1 Data exists in the reception buffer 5 SCnTBF Transmission buffer status indication 0 Transmission buffer empty 1 Data exists in the transmission buffer 6 SCnRXF Receptio...

Page 334: ...n SBT pin is an output only during transmission SCnTOE 0 it is necessary to pull up SBT pin In addition when using SBO pin as a data input output SCnMD0 1 it is necessary to pull up SBO pin Connect a pull up resistor externally When using SBO pin as a data output and SBI pin as a data input SCnMD0 0 the SBO pin is always an output and the SBI pin is always an input When using SBO pin as a data inp...

Page 335: ...ransfer the MSB bit 7 is ignored The SCnTXF flag is set to 1 when data is written to SCnTXB and is set to 0 at the end of transmission The SCnTBF flag is set to 1 when data is written to SCnTXB and is set to 0 at the start of transmission bp1 bp2 bp3 bp4 bp5 bp6 bp7 bp0 SBO pin SBT pin Data write SCnTXF flag SCnTBF flag Interrupt request when set to transmission buffer empty Interrupt request when...

Page 336: ...rocomputer side In this case interrupt requests are also generated by the transmission source Receive data according to the following procedure 1 Select the internal clock as the reference clock and set the parity character length etc 2 Enable both the transmission operation and the receiving operation 3 When dummy data is written to the transmission buffer the clock is sent and reception begins W...

Page 337: ...rrun error is generated when reception of the next data is completed before previously received data is read from the SCnRXB In this event the previously received data is lost The overrun error indicator flag SCnOEF is updated at the moment the final data bit is received A parity error is generated when 0 fixed parity is set and a 1 is received when 1 fixed parity is set and a 0 is received when e...

Page 338: ...that permits fast bit rates even with a clock source that operates at a comparatively low frequency Maximum bit rate 230 4 kbit s when IOCLK 15 MHz Error detection during reception Parity errors overrun errors flaming error Buffers Independent buffers for transmission and reception Reception and transmission buffers are both double buffers Interrupts Transmission interrupts Transmission end or tra...

Page 339: ...ock control IOCLK Timer 2 underflow Send break Transmission clock Reception buffer read Reception buffer Shift register Output control Interrupt request generation Transmission interrupt request Reception interrupt request Timer 8 underflow IRQ7 Serial interface 3 Transmission bit counter SC3ICR Interrupt mode register SC3TIM Timer register Reception bit counter SC3STR Status register SC3CTR Contr...

Page 340: ...col selection Table 13 4 1 List of UART Serial Interface Registers Address Name Symbol Number of bits Initial value Access size x 34000830 Serial 3 control register SC3CTR 16 x 0000 8 16 x 34000834 Serial 3 interrupt mode register SC3ICR 8 x 00 8 x 34000838 Serial 3 transmission buffer SC3TXB 8 x 00 8 x 34000839 Serial 3 reception buffer SC3RXB 8 x 00 8 x 3400083C Serial 3 status register SC3STR 8...

Page 341: ...R W R W R W R R R W R W R W R W R W R W R W R R W R W Bit No Bit name Description 0 SC3CK0 Clock source selection LSB 1 SC3CK1 Clock source selection MSB 00 IOCLK 01 Timer 2 underflow 10 External clock 11 Timer 8 underflow 2 0 is returned when this bit is read 3 SC3STB Stop bit selection 0 1 bit 1 2 bits 4 SC3PB0 Parity bit selection LSB 5 SC3PB1 Parity bit selection 6 SC3PB2 Parity bit selection ...

Page 342: ...om LSB 1 From MSB 11 to 10 0 is returned when this bit is read 12 SC3TWS Transmission interrupt code selection 0 Interrupt when external pin IRQ7 is L 1 Interrupt when external pin IRQ7 is H 13 SC3BKE Break transmission SBO3 pin is fixed at 0 0 Normal operation 1 Send break 14 SC3RXE Reception operation enable 0 Disabled 1 Enabled 15 SC3TXE Transmission operation enable 0 Disabled 1 Enabled ...

Page 343: ...No Bit name Description 0 SC3RI Reception interrupt factor selection 0 Reception end 1 Reception end with error 1 0 is returned when this bit is read 2 SC3RES Reception error interrupt factor selection 0 Interrupt request when an overrun parity or framing error occurs 1 Interrupt request when a parity error occurs 3 0 is returned when this bit is read 4 SC3TI Transmission interrupt factor selectio...

Page 344: ...cess R W R W R W R W R W R W R W R W Data is transmitted by writing it to this buffer Serial 3 reception buffer Register symbol SC3RXB Address x 34000839 Purpose This register reads in the reception data of serial interface 3 Bit No 7 6 5 4 3 2 1 0 Bit SC3 SC3 SC3 SC3 SC3 SC3 SC3 SC3 name RXB7 RXB6 RXB5 RXB4 RXB3 RXB2 RXB1 RXB0 Reset 0 0 0 0 0 0 0 0 Access R R R R R R R R Reception data is gotten ...

Page 345: ...error occurred 3 SC3CTS External pin IRQ7 status indication 0 when IRQ7 is L and 1 when H Note When P83A of the port 8 analog digital input control register P8AD is 1 IRQ7 is treated as L internally by the microcontroller and reading the SC3CTS bit returns a value of 0 regardless of the actual values of the port pins 4 SC3RBF Reception buffer status indication 0 Reception buffer empty 1 Data exist...

Page 346: ...s register sets the timer that is used for internal division for serial interface 3 Bit No 7 6 5 4 3 2 1 0 Bit SC3 SC3 SC3 SC3 SC3 SC3 SC3 name TIM6 TIM5 TIM4 TIM3 TIM2 TIM1 TIM0 Reset 0 0 0 0 0 0 0 0 Access R R W R W R W R W R W R W R W Set the value that corresponds to the required division ratio 1 ...

Page 347: ...r that supports fast bit rates even with a comparatively slow clock source For example when IOCLK is being used and a transfer is being performed the division ratio should be set as follows Note When an external clock signal is used as the clock source the high and low widths of the external clock must be at least 10 5 or 2 5 SYSCLK cycles when MCLK frequency SYSCLK frequency 1 2 or 4 respectively...

Page 348: ...or ABS division ratio 1 x division ratio 2 x bit rate IOCLK frequency 1 For example when a 15 MHz IOCLK signal is used and transfer is conducted at a rate of 38 4 kbit s the timer function is used to divide the clock signal According to the equations shown above division ratio 1 is 4 and division ratio 2 is 98 Set TM2BR 3 in the timer 2 base register and SC3TIM 97 in the serial 3 timer register an...

Page 349: ... 125 0 00 4 800 20 125 0 00 2 400 40 125 0 00 1 200 79 127 0 33 600 158 127 0 33 300 315 127 0 01 150 630 127 0 01 Table 13 4 4 Bit Rates 3 When IOCLK 8 MHz Bit rate bit s Division ratio 1 Division ratio 2 Bit rate error 230 400 1 35 0 80 115 200 1 69 0 64 56 000 2 71 0 60 38 400 2 104 0 16 19 200 4 104 0 16 9 600 7 119 0 04 4 800 14 119 0 04 2 400 27 123 0 37 1 200 53 126 0 17 600 105 127 0 01 30...

Page 350: ...at the transmission buffer is empty When writing either first confirm that the transmission buffer is empty by checking SC3TBF in the SC3STR status register and then write the data or else set SC3TI in the SC3ICR interrupt mode register to 1 and then write the data during the appropriate interrupt processing 3 Set a value of 16 or higher in SC3TIM 4 When using an external clock SBT3 pin the high a...

Page 351: ...ransfer the MSB bit 7 is ignored The SC3TXF flag is set to 1 when data is written to SC3TXB and is set to 0 at the end of transmission The SC3TBF flag is set to 1 when data is written to SC3TXB and is set to 0 at the start of transmission SBO pin Data write SC3TXF flag SC3TBF flag Interrupt request when set to transmission buffer empty Interrupt request when set to transmission end bp1 bp2 bp3 bp4...

Page 352: ...3RXB In the case of a 7 bit transfer the MSB bit 7 is 0 The SC3RXF flag is set to 1 at the start of reception when the start bit is detected and is set to 0 at the end of reception The SC3RBF flag is set to 1 at the end of reception and is set to 0 when SC3RXB is read SC3RXF flag SBI pin SC3RBF flag bp1 bp2 bp3 bp4 bp5 bp6 PTY bp0 ST SP Interrupt request Data read SP bp1 bp2 bp3 bp4 bp5 bp6 bp0 ST...

Page 353: ...n 0 fixed parity is set and a 1 is received when 1 fixed parity is set and a 0 is received when even parity is set and an odd number of ones is received or when odd parity is set and an even number of ones is received The parity error indicator flag SC3PEF is updated at the moment the parity bit is received A feaming error is generated when 0 was received for the stop bit The framing error indicat...

Page 354: ...Serial Interface 13 52 ...

Page 355: ...14 A D Converter 14 ...

Page 356: ... D converter that can process analog signals on a maximum of four channels The A D conversion reference clock can be selected from 1 2 1 4 1 8 or 1 16 of IOCLK When IOCLK 10 MHz A D conversion is performed with a maximum conversion speed of 2 8 µs ch 1 2 x IOCLK is selected as the A D conversion reference clock and the number of sampling cycles is 2 cycles Fig 14 1 1 A D Converter Configuration Di...

Page 357: ... 74 µs channel When IOCLK is 15 MHz conversion reference clock is 1 4 of IOCLK and the number of sampling cycles is 2 cycles Operating modes 14 modes Channel 0 one time conversion Channel 0 continuous conversion Channel 1 one time conversion Channel 1 continuous conversion Channel 0 to 1 one time conversion Channel 0 to 1 continuous conversion Channel 2 one time conversion Channel 2 continuous con...

Page 358: ...N2 AN3 ADTRG Selector Data buffer 10 bit x 4 ch Comparator A D interrupt request Interrupt generator Divider Shift registers for states A D conversion trigger Conversion reference clock Conversion results Conversion end Results writing Timer 2 underflow Data buffer selection For multiple channel conversion MC1 SC1 MC0 SC0 EN ST1 ST0 SHC CK1 CK0 MD1 MD0 ...

Page 359: ...C1 SC0 EN ST1 ST0 SHC CK1 CK0 MD1 MD0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit No Bit name Description 0 ADMD0 Operating mode selection LSB 1 ADMD1 Operating mode selection MSB 00 Any one channel one time conversion 01 Multiple channels one time conversion 10 Any one channel continuous conversion 11 Multiple channels continuou...

Page 360: ...B 13 ADMC1 Conversion channels when converting multiple channels MSB 00 AN0 01 AN0 to AN1 10 AN0 to AN2 11 AN0 to AN3 14 Must be set to 0 15 Must be set to 0 Note When a multiple number of channels are to be converted set 00 initially for ADSC1 to ADSC0 A Dn conversion data buffer n 0 1 2 3 Register symbol ADnBUF Address x 34000410 n 0 x 34000414 n 1 x 34000418 n 2 x 3400041C n 3 Purpose This regi...

Page 361: ...execution flag ADEN to 1 If the conversion start trigger selection bits ADST1 to 0 are set to external trigger then the conversion start execution flag ADEN is set to 1 when a falling edge is input to the ADTRG pin A D conversion then starts If the conversion start trigger selection bits ADST1 to 0 are set to timer trigger then the conversion start execution flag ADEN is set to 1 when a timer 2 un...

Page 362: ...ng edge is input to the ADTRG pin A D conversion then starts And if the conversion start trigger selection bits ADST1 to 0 are set to timer trigger then the conversion start execution flag ADEN is set to 1 when a timer 2 underflow occurs A D conversion then starts The conversion start execution flag ADEN is 1 while conversion is in progress and is then set to 0 after conversion of all channels is ...

Page 363: ...onversion start execution flag ADEN is set to 1 when a falling edge is input to the ADTRG pin A D conversion then starts And if the conversion start trigger selection bits ADST1 to 0 are set to timer trigger then the conversion start execution flag ADEN is set to 1 when a timer 2 underflow occurs A D conversion then starts The conversion start execution flag ADEN is 1 while conversion is in progre...

Page 364: ...election bits ADST1 to 0 are set to timer trigger then the conversion start execution flag ADEN is set to 1 when a timer 2 underflow occurs A D conversion then starts The conversion start execution flag ADEN is 1 while conversion is in progress and is not cleared by hardware Therefore set the conversion start execution flag ADEN to 0 when stopping the conversion operation The conversion channel se...

Page 365: ...ng When Using Four Sampling Cycles Set the conversion reference clock so that one cycle is at least 200 ns Set the number of sampling cycles so that one sampling cycle is at least 400 ns when the output impedance of the external device that drives the AN pin is 1 kΩ or less If the output impedance of the external device that drives the AN pin is greater than 1 kΩ it is necessary to lengthen the sa...

Page 366: ...ontinuous conversion The ADEN flag is set at the same time that ADST1 to 0 are switched and then A D conversion starts In the case of continuous conversion conversion is stopped by writing 0 to the ADEN flag Fig 14 5 8 Example of Conversion by Switching to External Trigger Mode Continuous Conversion Set b 00 or b 10 b 01 Reset automatically when conversion is completed External trigger input ADTRG...

Page 367: ...15 I O Ports 15 ...

Page 368: ... pins can be switched via the control register within the I O ports Port 0 P0 This port is also used for address bus signals A 22 20 and for the DRAM CAS signal CAS Port 1 P1 This port is also used for data bus signals D 7 0 the address strobe signal AS and read write select RWSEL Port 2 P2 This port is also used for data bus signals D 15 8 Port 3 P3 This port is also used for the bus grant signal...

Page 369: ...s port is also used for extension mode setting signals EXMOD1 and EXMOD0 memory write signals WE1 and WE0 memory read signal RE bus authority request signal BR data acknowledge signal DK and system clock SYSCLK Port A PA This port is also used for address bus signals A 7 0 and address data signals ADM 7 0 Port B PB This port is also used for address bus signals A 15 8 and address data signals ADM ...

Page 370: ...F 8 x 3600802C Port 6 output mode register P6MD 8 x 0F 8 16 x 3600802D Port 7 output mode register P7MD 8 x 00 8 x 36008030 Port 8 analog digital input control register P8AD 8 x 0F 8 16 x 36008031 Port 9 output mode register P9MD 8 x 60 8 x 36008034 Port A output mode register PAMD 8 x 00 x 02 8 16 x 36008035 Port B output mode register PBMD 8 x 00 x 02 8 x 36008038 Port C output mode register PCM...

Page 371: ...r P2IN 8 x XX 8 16 x 36008085 Port 3 pin register P3IN 8 x 0X 8 x 36008088 Port 4 pin register P4IN 8 x XX 8 16 x 36008089 Port 5 pin register P5IN 8 x XX 8 x 3600808C Port 6 pin register P6IN 8 x 0X 8 x 36008090 Port 8 pin register P8IN 8 x 0X 8 16 x 36008091 Port 9 pin register P9IN 8 x XX 8 x 36008094 Port A pin register PAIN 8 x XX 8 16 x 36008095 Port B pin register PBIN 8 x XX 8 ...

Page 372: ...d Fig 15 2 2 show block diagrams for port 0 Fig 15 2 1 Port 0 Block Diagram P02 Internal data bus P02 P0OUT P02O P Represents one bit of each register M P X CAS A22 M P X P02MD P0MD P02S P0SS A23 to A16 Output enable signals Output control Control signal from BC ...

Page 373: ...ter for port 0 is described below Port 0 output register Register symbol P0OUT Address x 36008000 Purpose This register sets the data to be output on port 0 Bit No 7 6 5 4 3 2 1 0 Bit name P02O P01O P00O Reset 0 0 0 0 0 0 0 0 Access R R R R R R W R W R W Internal data bus P0n n 1 0 P0OUT P0nO P Represents one bit of each register M P X A21 n 1 P0nMD P0MD A23 to A16 Output enable signals A20 n 0 ...

Page 374: ...ted output control register Register symbol P0SS Address x 36008040 Purpose This register selects the content output on the port 0 pins Valid when the P0nMD bit is 0 Bit No 7 6 5 4 3 2 1 0 Bit name P02S Reset 0 0 0 0 0 0 0 0 Access R R R R R R W R R P02MD P02S 00 Address output A22 01 DRAM CAS signal output for 2WE CAS 1x General purpose output port P02 P01MD 0 Address output A21 1 General purpose...

Page 375: ...0 Port 0 100 P00 General purpose output port A20 Address output 99 P01 General purpose output port A21 Address output 97 P02 General purpose output port CAS DRAM CAS signal output for 2WE A22 Address output Note 1 When reset whether in address data separate mode or address data multiplex mode Note 2 When the bus authority is granted CAS and A22 to A20 go to high impedance ...

Page 376: ...and 15 3 2 show block diagrams for port 1 Fig 15 3 1 Port 1 Block Diagram P17 to P12 Internal data bus M P X P1n n 7 6 5 4 3 2 P1OUT D7 n 7 to D2 n 2 P1M P1MD P1DIR P1nD P1nO P Represents one bit of each register M P X P1PU P1nI P1IN D7 to D0 Output enable signal ...

Page 377: ...nd P10 Internal data bus M P X P1OUT P1nO D1 n 1 D0 n 0 P1M P1MD P1DIR P1nD P Represents one bit of each register M P X P1PU P1nI P1IN D7 to D0 Output enable signal P1n n 1 0 RWSEL n 1 AS n 0 M P X M P X Address data multiplex mode Control Signal from BC ...

Page 378: ...ter symbol P1OUT Address x 36008001 Purpose This register sets the data to be output on port 1 Bit No 7 6 5 4 3 2 1 0 Bit name P17O P16O P15O P14O P13O P12O P11O P10O Reset 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W Port 1 pin register Register symbol P1IN Address x 36008081 Purpose This register reads the values of the port 1 pins Bit No 7 6 5 4 3 2 1 0 Bit name P17I P16I P15I P14I P1...

Page 379: ...1 the port 1 pins are set as a general purpose port when P1M is 0 the port 1 pins are set as data pins When P1PU is 1 the port 1 pins are pulled up Note The setting of P1PU that pulls up or does not pull up the port 1 pins can be made regardless of the value of P1M Bit No 7 6 5 4 3 2 1 0 Bit name P1PU P1M Reset 0 0 0 0 0 0 1 0 0 1 Access R R R R R R R W R W are set in address data multiplex mode I...

Page 380: ...tput port General purpose input port D5 1 Data input output 89 P16 General purpose output port General purpose input port D6 1 Data input output 88 P17 General purpose output port General purpose input port D7 1 Data input output Note 1 When reset in address data separate mode General purpose input port is selected in address data multiplex mode pin No 95 and 96 however are set as RWSEL and AS res...

Page 381: ... shows a block diagrams for port 2 Fig 15 4 1 Port 2 Block Diagram P27 to P20 Internal data bus M P X P2n n 7 6 5 4 3 2 1 0 P2OUT D15 n 7 to D8 n 0 P2M P2MD P2DIR P2nD P2nO P Represents one bit of each register M P X P2PU P2nI P2IN D15 to D8 output enable signal ...

Page 382: ... 36008004 Purpose This register sets the data to be output on port 2 Bit No 7 6 5 4 3 2 1 0 Bit name P27O P26O P25O P24O P23O P22O P21O P20O Reset 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W Port 2 pin register Register symbol P2IN Address x 36008084 Purpose This register reads the values of the port 2 pins Bit No 7 6 5 4 3 2 1 0 Bit name P27I P26I P25I P24I P23I P22I P21I P20I Reset X ...

Page 383: ...r Register symbol P2MD Address x 36008024 Purpose When P2M is 1 the port 2 pins are set as a general purpose port when P2M is 0 the port 2 pins are set as data pins When P2PU is 1 the port 2 pins are pulled up Note The setting of P2PU that pulls up or does not pull up the port 2 pins can be made regardless of the value of P2M Bit No 7 6 5 4 3 2 1 0 Bit name P2PU P2M Reset 0 0 0 0 0 0 1 0 0 1 Acces...

Page 384: ...urpose output port General purpose input port D12 1 Data input output 80 P25 General purpose output port General purpose input port D13 1 Data input output 78 P26 General purpose output port General purpose input port D14 1 Data input output 77 P27 General purpose output port General purpose input port D15 1 Data input output Note 1 When reset in address data separate mode General purpose input po...

Page 385: ...Port 3 15 5 1 Block Diagram Fig 15 5 1 shows a block diagram for port 3 Fig 15 5 1 Port 3 Block Diagram P30 Internal data bus M P X P30 P3OUT P3M P3MD P3DIR P30D P30O P Represents one bit of each register M P X P30I P3IN BG ...

Page 386: ... 6 5 4 3 2 1 0 Bit name P30O Reset 0 0 0 0 0 0 0 0 Access R R R R R R R R W Port 3 pin register Register symbol P3IN Address x 36008085 Purpose This register reads the value of the port 3 pin Bit No 7 6 5 4 3 2 1 0 Bit name P30I Reset 0 0 0 0 0 0 0 X Access R R R R R R R R Port 3 input output control register Register symbol P3DIR Address x 36008065 Purpose This register sets the port 3 pin for in...

Page 387: ...selected in the P3MD register this control signal is output regardless of the value in the P3DIR register The input output settings for this general purpose port are made through the P3DIR register 15 5 3 Pin Configurations Table 15 5 1 shows the pin configurations for port 3 Table 15 5 1 Port 3 Configuration Port Pin P3n P3M 1 P3M 0 No P30D 1 P30D 0 Port 3 76 P30 General purpose output port Gener...

Page 388: ...g 15 6 1 Port 4 Block Diagram P45 and P43 P4n n 5 3 Internal data bus P4OUT P4nI P4IN P4nM P4MD P4DIR P4nD P4nO P Represents one bit of each register P4nS P4SS M P X M P X DWE n 5 DCAS0 n 3 SBO1 n 5 SBT1 n 3 SBO1 n 5 SBT1 n 3 SBO1 output enable n 5 SBT1 output enable n 3 M P X M P X Control signal from BC ...

Page 389: ...ts 15 23 Fig 15 6 2 Port 4 Block Diagram P44 Internal data bus P44 P4OUT P44I P4IN P44M P4MD P4DIR P44D P44O P Represents one bit of each register P44S P4SS M P X M P X DCAS1 SBI1 M P X Control signal from BC ...

Page 390: ...l data bus P4n n 2 0 P4OUT P4DIR P4nD P4nO P Represents one bit of each register M P X M P X P4nI P4IN P4nM P4MD SBO0 n 2 SBT0 n 0 SBO0 output enable n 2 SBT0 output enable n 0 SBO0 n 2 SBT0 n 0 Internal data bus P Represents one bit of each register P4OUT P41O P41 P4DIR P41D P41I P4IN P41M P4MD SBI0 ...

Page 391: ...ort 4 is described below Port 4 output register Register symbol P4OUT Address x 36008008 Purpose This register sets the data to be output on port 4 Bit No 7 6 5 4 3 2 1 0 Bit name P45O P44O P43O P42O P41O P40O Reset 0 0 0 0 0 0 0 0 Access R R R W R W R W R W R W R W Port 4 pin register Register symbol P4IN Address x 36008088 Purpose This register reads the value of the port 4 pins Bit No 7 6 5 4 3...

Page 392: ...7 6 5 4 3 2 1 0 Bit name P45D P44D P43D P42D P41D P40D Reset 0 0 0 0 0 0 0 0 Access R R R W R W R W R W R W R W Port 4 output mode register Register symbol P4MD Address x 36008028 Purpose Along with P4SS this register selects the content output on the port 4 pins Bit No 7 6 5 4 3 2 1 0 Bit name P45M P44M P43M P42M P41M P40M Reset 0 0 1 1 1 1 1 1 Access R R R W R W R W R W R W R W ...

Page 393: ...ial 1 transfer clock input output SBT1 The input output setting is made through the serial interface 1 settings 01 DRAM CAS signal 0 output for 2CAS DCAS0 1x General purpose input output port P43 P42M 0 Serial 0 data input output SBO0 The input output setting is made through the serial interface 0 settings 1 General purpose input output port P42 P41M 0 Serial 0 data input SBI0 1 General purpose in...

Page 394: ...BT1 2 Serial 1 transfer output port input port output for 2CAS clock input output 70 P44 General purpose General purpose DCAS1 DRAM CAS signal 1 SBI1 Serial 1 output port input port output for 2CAS data input 68 P45 General purpose General purpose DWE DRAM write signal SBO1 2 Serial 1 output port input port output for 2CAS data input output Note 1 When reset whether in address data separate mode o...

Page 395: ... Figs 15 7 1 to 15 7 5 show block diagrams for port 5 Fig 15 7 1 Port 5 Block Diagram P55 Internal data bus P5OUT P55O TM13IO M P X P55 M P X P Represents one bit of each register P55I P5IN TM13IO TM5IO TM5IO P5DIR P55D P55M P5MD P55S P5SS M P X SBO3 ...

Page 396: ...orts 15 30 Fig 15 7 2 Port 5 Block Diagram P54 Internal data bus P5OUT P54O TM12IO M P X P54 M P X P Represents one bit of each register P54I P5IN TM12IO TM4IO SBI3 TM4IO P5DIR P54D M P X P54M P5MD P54S P5SS ...

Page 397: ...orts 15 31 Fig 15 7 3 Port 5 Block Diagram P53 Internal data bus P5OUT P53O TM11IO M P X P53 M P X P Represents one bit of each register P53I P5IN TM11IO TM3IO SBT3 TM3IO P5DIR P53D M P X P53M P5MD P53S P5SS ...

Page 398: ...P50 P5n n 2 0 Internal data bus P5OUT P5DIR P5nD P5nO P Represents one bit of each register M P X M P X TM2IO n 2 SBO2 n 2 SBO2 output enable n 2 SBT2 output enable n 0 M P X P5nI P5IN TM2IO SBO2 n 2 TM0IO SBT2 n 0 TM0IO n 0 SBT2 n 0 P5nM P5MD P5nS P5SS ...

Page 399: ...I O Ports 15 33 Fig 15 7 5 Port 5 Block Diagram P51 Internal data bus TM1IO P5OUT P51O M P X TM1IO SBI2 P51 P Represents one bit of each register P51I P5IN P5DIR P51D M P X P51M P5MD P51S P5SS ...

Page 400: ... for port 5 is described below Port 5 output register Register symbol P5OUT Address x 36008009 Purpose This register sets the data to be output on port 5 Bit No 7 6 5 4 3 2 1 0 Bit name P55O P54O P53O P52O P51O P50O Reset 0 0 0 0 0 0 0 0 Access R R R W R W R W R W R W R W Port 5 pin register Register symbol P5IN Address x 36008089 Purpose This register reads the value of the port 5 pins Bit No 7 6...

Page 401: ...7 6 5 4 3 2 1 0 Bit name P55D P54D P53D P52D P51D P50D Reset 0 0 0 0 0 0 0 0 Access R R R W R W R W R W R W R W Port 5 output mode register Register symbol P5MD Address x 36008029 Purpose Along with P5SS this register selects the content output on the port 5 pins Bit No 7 6 5 4 3 2 1 0 Bit name P55M P54M P53M P52M P51M P50M Reset 0 0 1 1 1 1 1 1 Access R R R W R W R W R W R W R W ...

Page 402: ...3M P53S 00 Serial 3 transfer clock input SBT3 01 Timer input output TM3IO 8 bit timer 10 Timer input output TM11IO 16 bit timer 11 General purpose input output port P53 P52M P52S 00 Serial 2 data input output SBO2 The input output settings depend on the serial interface 2 settings and the timing 01 Timer input output TM2IO 8 bit timer 1x General purpose input output port P52 P51M P51S 00 Serial 2 ...

Page 403: ...11 TM3IO Timer 3 Timer 3 SBT3 Serial 3 purpose purpose output input or timer or timer B 6 transfer output port input port B output input clock input 4 63 P54 General General TM12IO Timer 12 Timer 12 TM4IO Timer 4 Timer 4 SBI3 Serial 3 purpose purpose output input output input data input output port input port 62 P55 General General TM13IO Timer 13 Timer 13 TM5IO Timer 5 Timer 5 SBO3 Serial 3 purpo...

Page 404: ... for port 6 Fig 15 8 1 Port 6 Block Diagram P63 to P60 Internal data bus P6OUT P6nO M P X P6n n 3 2 1 0 P6DIR P6nD P Represents one bit of each register P6nI P6IN P6nM P6MD TM10IOB n 3 TM10IOA n 2 TM7IO n 1 TM6IO n 0 ADTRG IRQ3 TM10IOB n 3 IRQ2 TM10IOA n 2 IRQ1 TM7IO n 1 IRQ0 TM6IO n 0 ...

Page 405: ... be output on port 6 Bit No 7 6 5 4 3 2 1 0 Bit name P63O P62O P61O P60O Reset 0 0 0 0 0 0 0 0 Access R R R R R W R W R W R W Port 6 pin register Register symbol P6IN Address x 3600808C Purpose This register reads the value of the port 6 pins Bit No 7 6 5 4 3 2 1 0 Bit name P63I P62I P61I P60I Reset 0 0 0 0 X X X X Access R R R R R R R R Port 6 input output control register Register symbol P6DIR A...

Page 406: ...P6nD 1 P6nD 0 Port 6 59 P60 General purpose output port General purpose input port TM6IO Timer 6 output Timer 6 input 58 P61 General purpose output port General purpose input port TM7IO Timer 7 output Timer 7 input 57 P62 General purpose output port General purpose input port TM10IOA Timer 10 output A Timer 10 input A 56 P63 General purpose output port General purpose input port TM10IOB Timer 10 o...

Page 407: ...gram P73 Fig 15 9 2 Port 7 Block Diagram P72 to P70 Internal data bus P7OUT P7nO M P X P7n n 2 1 0 P7MD P Represents one bit of each register P7nM CS2 RAS2 n 2 Controlsignal fromBC CS1 RAS1 n 1 CS0 n 0 Internal data bus P7OUT P73O P73 P7SS P Represents one bit of each register P73S A23 Control signal from BC M P X P7MD P73M M P X CS3 ...

Page 408: ...egister Register symbol P7OUT Address x 3600800D Purpose This register sets the data to be output on port 7 Bit No 7 6 5 4 3 2 1 0 Bit name P73O P72O P71O P70O Reset 0 0 0 0 0 0 0 0 Access R R R R R W R W R W R W Port 7 output mode register Register symbol P7MD Address x 3600802D Purpose This register selects the content output on the port 7 pins Bit No 7 6 5 4 3 2 1 0 Bit name P73M P72M P71M P70M...

Page 409: ...port P73 P72M 0 Chip select signal 2 output DRAM RAS signal 2 output CS2 RAS2 The CS2 RAS2 selection depends on the setting of the registers within the bus controller 1 General purpose output port P72 Note For details on the bus controller register settings refer to section 8 6 Description of Registers P71M 0 Chip select signal 1 output DRAM RAS signal 1 output CS1 RAS1 The CS1 RAS1 selection depe...

Page 410: ...output 51 P73 General purpose output port A23 Address output CS3 Chip select signal 3 output Note 1 When reset whether in address data separate mode or address data multiplex mode 1 If block 1 in the external memory space is not used as a DRAM space CS1 is selected if block 1 is used as a DRAM space RAS1 is selected 2 If block 2 in the external memory space is not used as a DRAM space CS2 is selec...

Page 411: ... Block Diagram Figs 15 10 1 shows the block diagrams for port 8 Fig 15 10 1 Port 8 Block Diagram P83 to P80 Internal data bus P8n n 3 2 1 0 P Represents one bit of each register AN3 n 3 to AN0 n 0 P8nA P8AD P8nI P8IN IRQ7 n 3 to IRQ4 n 0 ...

Page 412: ... 0 digital 1 analog Bit No 7 6 5 4 3 2 1 0 Bit name P83A P82A P81A P80A Reset 0 0 0 0 1 1 1 1 Access R R R R R W R W R W R W Port 8 pin register Register symbol P8IN Address x 36008090 Purpose This register reads the value of the port 8 pins Bit No 7 6 5 4 3 2 1 0 Bit name P83I P82I P81I P80I Reset 0 0 0 0 X X X X Access R R R R R R R R When P8nA is 1 reading this register returns a value of 0 reg...

Page 413: ...81 General purpose input port AN1 Analog signal input 46 P82 General purpose input port AN2 Analog signal input 45 P83 General purpose input port AN3 Analog signal input Note 1 When reset whether in address data separate mode or address data multiplex mode Note 2 When pin Nos 45 to 48 respectively are set as external interrupt input pins IRQ7 to IRQ4 the pins must be set as a general purpose input...

Page 414: ...iagrams for port 9 Fig 15 11 1 Port 9 Block Diagram P97 Fig 15 11 2 Port 9 Block Diagram P96 Internal data bus P9OUT P97O M P X P97 P Represents one bit of each register P97M P9MD SYSCLK Internal data bus P Represents one bit of each register P9OUT P96O P96 P9DIR P96D P96I P9IN P96M P9MD BR ...

Page 415: ...am P94 P93 P92 Internal data bus P Represents one bit of each register P9OUT P9nO P9n n 5 1 0 P9DIR P9nD P9nI P9IN P9nM P9MD DK n 5 EXMOD1 n 1 EXMOD0 n 0 Internal data bus P9OUT P9nO M P X P9n n 4 3 2 P9MD P Represents one bit of each register P9nM WE1 n 4 Controlsignal fromBC WE0 n 3 RE n 2 ...

Page 416: ...e This register sets the data to be output on port 9 Bit No 7 6 5 4 3 2 1 0 Bit name P97O P96O P95O P94O P93O P92O P91O P90O Reset 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W Port 9 pin register Register symbol P9IN Address x 36008091 Purpose This register reads the value of the port 9 pins Bit No 7 6 5 4 3 2 1 0 Bit name P96I P95I P91I P90I Reset 0 X X 0 0 0 X X Access R R R R R R R R ...

Page 417: ...output port P96 P95M 0 Data acknowledge signal input DK 1 General purpose input output port P95 P94M 0 Memory write signal output WE1 1 General purpose output port P94 P93M 0 Memory write signal output WE0 1 General purpose output port P93 P92M 0 Memory read signal output RE 1 General purpose output port P92 P91M 1 General purpose input output port P91 P90M 1 General purpose input output port P90 ...

Page 418: ...urpose output port RE Memory read signal output 39 P93 General purpose output port WE0 Memory write signal output 38 P94 General purpose output port WE1 Memory write signal output 37 P95 General purpose output port General purpose input port DK Data acknowledge signal input 36 P96 General purpose output port General purpose input port BR Bus authority request signal input 34 P97 General purpose ou...

Page 419: ...lock diagram for port A Fig 15 12 1 Port A Block Diagram PA7 to PA0 Internal data bus M P X PAn n 7 6 5 4 3 2 1 0 PAOUT A7 n 7 to A0 n 0 PAM PAMD PADIR PAnD PAnO P Represents one bit of each register M P X PAPU PAnI PAIN A7 to A0 Output enable signal ADM7 n 7 to ADM0 n 0 or ...

Page 420: ...bol PAOUT Address x 36008014 Purpose This register sets the data to be output on port A Bit No 7 6 5 4 3 2 1 0 Bit name PA7O PA6O PA5O PA4O PA3O PA2O PA1O PA0O Reset 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W Port A pin register Register symbol PAIN Address x 36008094 Purpose This register reads the value of the port A pins Bit No 7 6 5 4 3 2 1 0 Bit name PA7I PA6I PA5I PA4I PA3I PA2I ...

Page 421: ...W R W R W R W R W R W Port A output mode register Register symbol PAMD Address x 36008034 Purpose When PAM is 1 the port A pins are set as a general purpose port when PAM is 0 the port A pins are set as address pins When PAPU is 1 the port A pins are pulled up Note The setting of PAPU that pulls up or does not pull up the port A pins can be made regardless of the value of PAM Bit No 7 6 5 4 3 2 1 ...

Page 422: ...19 PA4 General purpose General purpose A4 Address output output port input port ADM4 1 Address data input output 18 PA5 General purpose General purpose A5 Address output output port input port ADM5 1 Address data input output 17 PA6 General purpose General purpose A6 Address output output port input port ADM6 1 Address data input output 16 PA7 General purpose General purpose A7 Address output outp...

Page 423: ...ck diagram for port B Fig 15 13 1 Port B Block Diagram PB7 to PB0 Internal data bus M P X PBn n 7 6 5 4 3 2 1 0 PBOUT A15 n 7 to A8 n 0 PBM PBMD PBDIR PBnD PBnO P Represents one bit of each register M P X PBPU PBnI PBIN A15 to A8 output enable signal ADM15 n 7 to ADM8 n 0 or ...

Page 424: ...mbol PBOUT Address x 36008015 Purpose This register sets the data to be output on port B Bit No 7 6 5 4 3 2 1 0 Bit name PB7O PB6O PB5O PB4O PB3O PB2O PB1O PB0O Reset 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W Port B pin register Register symbol PBIN Address x 36008095 Purpose This register reads the value of the port B pins Bit No 7 6 5 4 3 2 1 0 Bit name PB7I PB6I PB5I PB4I PB3I PB2I...

Page 425: ... R W R W R W R W R W Port B output mode register Register symbol PBMD Address x 36008035 Purpose When PBM is 1 the port B pins are set as a general purpose port when PBM is 0 the port B pins are set as address pins When PBPU is 1 the port B pins are pulled up Note The setting of PBPU that pulls up or does not pull up the port B pins can be made regardless of the value of PBM Bit No 7 6 5 4 3 2 1 0...

Page 426: ... PB4 General purpose General purpose A12 Address output output port input port ADM12 1 Address data input output 8 PB5 General purpose General purpose A13 Address output output port input port ADM13 1 Address data input output 7 PB6 General purpose General purpose A14 Address output output port input port ADM14 1 Address data input output 6 PB7 General purpose General purpose A15 Address output ou...

Page 427: ...gram Fig 15 14 1 shows a block diagram for port C Fig 15 14 1 Port C Block Diagram PC3 to PC0 Internal data bus M P X PCn n 3 2 1 0 PCOUT PCnM PCMD PCnO M P X A23 to A16 Output enable signal A19 n 3 to A16 n 0 P Represents one bit of each register ...

Page 428: ...O PC1O PC0O Reset 0 0 0 0 0 0 0 0 Access R R R R R W R W R W R W Port C output mode register Register symbol PCMD Address x 36008038 Purpose This register selects the content output on the port C pins Bit No 7 6 5 4 3 2 1 0 Bit name PC3M PC2M PC1M PC0M Reset 0 0 0 0 0 0 0 0 Access R R R R R W R W R W R W PC3M 0 Address output A19 1 General purpose output port PC3 PC2M 0 Address output A18 1 Genera...

Page 429: ...5 PC0 General purpose output port A16 Address output 4 PC1 General purpose output port A17 Address output 2 PC2 General purpose output port A18 Address output 1 PC3 General purpose output port A19 Address output Note 1 When reset whether in address data separate mode or address data multiplex mode Note 2 When the bus authority is granted A19 to A16 go to high impedance ...

Page 430: ...ors or set as output port and leave open Either set as input port and connect to VDD or VSS via individual resistors or else use the built in pull up resistance by setting the register appropriately or set as output port and leave open Set as port and leave open PC3 A19 PC2 A18 PC1 A17 PC0 A16 PB7 ADM15 A15 PB6 ADM14 A14 PB5 ADM13 A13 PB4 ADM12 A12 PB3 ADM11 A11 PB2 ADM10 A10 PB1 ADM9 A9 PB0 ADM8 ...

Page 431: ...16 Internal Flash Memory 16 ...

Page 432: ...re area and erasure of individual 8 KB blocks 8 byte page program permits fast data writing Supports two flash memory overwrite modes flash memory mode and on board write mode On board write mode includes mechanisms designed to prevent accidental erasure or writing of flash memory 16 3 Block Diagram Fig 16 3 1 shows the block diagram of flash memory and related blocks Fig 16 3 1 Flash Memory Block...

Page 433: ...ins On board write mode is used to overwrite the internal flash memory via software This makes it possible to overwrite the internal flash memory while the microcontroller is still mounted on a board The address data separate mode or address data multiplex mode may apply as the on board write mode Table 16 4 1 Mode Settings through the External Pins Mode name MMOD1 MMOD0 EXMOD1 EXMOD0 Flash memory...

Page 434: ...NROMRST PD15 PD14 VDD PD13 PD12 PD11 PD9 VSS VPP PD8 PD7 PD6 PD5 PD4 VDD PD3 PD2 PD1 PD10 PD0 E VSS TEST3 TEST2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 TEST1 TEST0 VDD PA17 PA16 PA15 PA14 PA13 VSS PA12 PA11 PA10 PA9 PA8 VDD PA7 PA6 PA5 PA4 PA3 VSS PA2 PA1 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VSS VDD VSS VDD PVSS PVDD MMOD1 MMOD0 RST V...

Page 435: ... 81 PD12 I O 7 PA14 I 32 H 57 O 82 PD11 I O 8 PA13 I 33 VDD 58 O 83 PD10 I O 9 VSS 34 O 59 O 84 PD9 I O 10 PA12 I 35 VSS 60 VSS 85 VSS 11 PA11 I 36 H 61 O 86 VPP 12 PA10 I 37 H 62 O 87 PD8 I O 13 PA9 I 38 H 63 O 88 PD7 I O 14 PA8 I 39 NWE I 64 O 89 PD6 I O 15 VDD 40 NOE I 65 O 90 PD5 I O 16 PA7 I 41 VDD 66 O 91 PD4 I O 17 PA6 I 42 EXMOD1 L 67 O 92 VDD 18 PA5 I 43 EXMOD0 H 68 O 93 PD3 I O 19 PA4 I ...

Page 436: ...s low for at least 1 ms to the reset pin NROMRST Pin Name Input Output Description PA 17 1 Input Address PD 15 0 Input Output Data NCE Chip enable MODE Mode NOE Output enable NWE Write enable E Erase enable FROM Flash memory microcontroller mode switch TEST 3 0 Test signal Input x 0 NROMRST Reset VDD Power supply VPP Power supply VSS Power supply Input Input Input Input Input Input Input Input ...

Page 437: ... 8 KB Erasure block 7 8 KB Erasure block 8 8 KB Erasure block 9 x 0A000 x 0C000 x 0E000 x 10000 x 12000 8 KB Erasure block 10 8 KB Erasure block 11 8 KB Erasure block 12 8 KB Erasure block 13 8 KB Erasure block 14 x 14000 x 16000 x 18000 x 1A000 x 1C000 8 KB Erasure block 15 x 1E000 x 1FFFF EBR0 EBR1 EBR2 EBR3 EBR4 EBR5 EBR6 EBR7 EBR8 EBR9 EBR10 EBR11 EBR12 EBR13 EBR14 EBR15 Erasure block register...

Page 438: ...set for other signals by the I O port register settings they operate in accordance with the register settings Design the board of any external device that is to be connected to above signal pins in such a way that no difficulty will be encountered even if the above signal pins do operate AS RWSEL ADM 15 0 Address data separate A 12 0 D 15 0 Address data multiplex Address Registername Symbol Number...

Page 439: ...17 17 Ordering Mask ROM ...

Page 440: ...le interrupt processing routine This is not necessary if non maskable interrupts are not being used however When using this method however the program must be relocatable Ordering method 2 Refer to Fig 17 2 2 Rewrite the loader program so that the user program executes without referencing the flash memory mode register FLMODR Because the execution address after a reset state is released is x 40000...

Page 441: ...000 x 40002000 User program User program Loader program 8 KB x 40002000 x 40000008 JMP x 40002000 JMP x 40002008 8 KB When the user program starts in x 40002000 and the non maskable interrupt processing routine starts in x 40002008 Program in flash memory Program in mask ROM ...

Page 442: ...Ordering Mask ROM 17 4 ...

Page 443: ...Appendix ...

Page 444: ...CR G13ICR x 3400041X G19ICR G18ICR G16ICR G17ICR x 3400013X x 3200003X x 2000000X Address CPU Memory control Interrupts MEMCTRC x 2000002X CPUM x 2000004X IVAR1 IVAR2 IVAR3 IVAR4 x 2000001X IVAR5 IVAR6 1 2 3 4 5 6 7 8 9 A B C D E F MEMCTR0A MEMCTR1A MEMCTR2A MEMCTR3A DRAMCTR CKCTR REFCNT ADCTR AD0BUF A D AD1BUF AD2BUF AD3BUF IAGR EXTMD x 3200002X PRAR Note Accessing areas that are not mounted is p...

Page 445: ...TM5 CMP TM6 MD TM6 BR TM6 BC TM6 CMP TM7 MD TM7 BR TM7 BC TM7 CMP TM8 MD TM8 BR TM8 BC TM8 CMP TM9 MD TM9 BR TM9 BC TM9 CMP TMA MD TMA BR TMA BC TMA CMP TMB MD TMB BR TMB BC TMB CMP TM3 MD TM3 BR TM3 BC TM2 MD TM2 BR TM2 BC TM1 MD TM1 BC TM1 BR TMPS CNT TM10MD TM11BR TM10BC TM11BC TM11 MD TM12BR TM12BC TM12 MD TM13BR TM13BC TM13 MD TM10 MDB TM10CA TM10CB RST CTR WDBC WDCTR FCREG FBEWER FAREG FAREG...

Page 446: ...00805X x 3600806X x 3600807X x 3600808X x 3600809X P0OUT P3OUT PAOUT P2OUT P2MD P3MD PAMD PBMD P5SS P2DIR P3DIR P2IN P3IN P5OUT P4OUT P4MD P5MD P4SS P4DIR P5DIR P4IN P7OUT P6OUT P6MD P7MD P7SS P6DIR P6IN P5IN PBOUT PCOUT P9MD PCMD P1IN PBDIR PADIR PAIN PBIN Note Accessing areas that are not mounted is prohibited Operation is not guaranteed if an area that is not mounted is accessed ...

Page 447: ...16 Dn S2 3 1 MOV abs32 Dn D4 6 2 MOV Am An D0 2 1 MOV d8 Am An D1 3 1 MOV d16 Am An D2 4 1 MOV d32 Am An D4 6 2 MOV d8 SP An S1 2 1 MOV d16 SP An D2 4 1 MOV d32 SP An D4 6 2 MOV Di Am An D0 2 1 MOV abs16 An D2 4 1 MOV abs32 An D4 6 2 MOV d8 Am SP D1 3 1 MOV Dm An S0 1 1 MOV Dm d8 An D1 3 1 MOV Dm d16 An D2 4 1 MOV Dm d32 An D4 6 2 MOV Dm d8 SP S1 2 1 MOV Dm d16 SP D2 4 1 MOV Dm d32 SP D4 6 2 MOV D...

Page 448: ...0 2 1 MOVHU abs16 Dn S2 3 1 MOVHU abs32 Dn D4 6 2 MOVHU Dm An D0 2 1 MOVHU Dm d8 An D1 3 1 MOVHU Dm d16 An D2 4 1 MOVHU Dm d32 An D4 6 2 MOVHU Dm d8 SP D1 3 1 MOVHU Dm d16 SP D2 4 1 MOVHU Dm d32 SP D4 6 2 MOVHU Dm Di An D0 2 2 MOVHU Dm abs16 S2 3 1 MOVHU Dm abs32 D4 6 2 EXT EXT Dn D0 2 1 EXTB EXTB Dn S0 1 1 EXTBU EXTBU Dn S0 1 1 EXTH EXTH Dn S0 1 1 EXTHU EXTHU Dn S0 1 1 MOVM MOVM SP regs S1 2 1 Re...

Page 449: ...is a value which can be expressed with 4 bytes MULU MULU Dm Dn D0 2 3 Dn 0 13 Dn is a value which can be expressed with 1 byte 21 Dn is a value which can be expressed with 2 bytes 29 Dn is a value which can be expressed with 3 bytes 34 Dn is a value which can be expressed with 4 bytes DIV DIV Dm Dn D0 2 4 MDR Dn 0 14 22 30 38 DIVU DIVU Dm Dn D0 2 4 MDR Dn 0 14 22 30 38 INC INC Dn S0 1 1 INC An S0 ...

Page 450: ...2 3 1 Branching taken not taken BNE d8 PC S1 2 3 1 Branching taken not taken BGT d8 PC S1 2 3 1 Branching taken not taken BGE d8 PC S1 2 3 1 Branching taken not taken BLE d8 PC S1 2 3 1 Branching taken not taken BLT d8 PC S1 2 3 1 Branching taken not taken BHI d8 PC S1 2 3 1 Branching taken not taken BCC d8 PC S1 2 3 1 Branching taken not taken BLS d8 PC S1 2 3 1 Branching taken not taken BCS d8 P...

Page 451: ...3 CALLS d32 PC D4 6 4 RET RET regs imm8 S2 3 4 Registers specified by regs 0 4 Registers specified by regs 1 4 Registers specified by regs 2 4 Registers specified by regs 3 5 Registers specified by regs 4 8 Registers specified by regs 7 9 Registers specified by regs 8 10 Registers specified by regs 9 11 Registers specified by regs 10 12 Registers specified by regs 11 RETF RETF regs imm8 S2 3 2 Reg...

Page 452: ...byte or imm 0 6 imm is a value which can be expressed with 4 bytes to 3 bytes MULQU MULQU Dm Dn D0 2 4 Dm is a value which can be expressed with 2 bytes to 1 byte or Dm 0 5 Dm is a value which can be expressed with 4 bytes to 3 bytes MULQIU imm8 Dn D1 3 4 MULQIU imm16 Dn D2 4 4 MULQIU imm32 Dn D4 6 5 imm is a value which can be expressed with 2 bytes to 1 byte or imm 0 6 imm is a value which can b...

Page 453: ... 16 bits 2 CAS control Block 2 8 bit bus 1 Mbit SRAM 131 072 words x 8 bits Fig C 1 Memory Connection Example Note Fig C 1 is provided as a reference example and is not intended to guarantee operation WE0 MN103001G MN1030F01K RE A 23 0 DWE DCAS 1 0 RAS1 CS2 D 15 0 A 17 0 D 15 0 CE OE 4 Mbit ROM CS0 D 15 0 A 18 1 A 8 0 D 15 0 RAS LCAS OE WE 4 Mbit DRAM A 16 0 D 7 0 CE OE WE 1 Mbit SRAM UCAS DCAS 1 ...

Page 454: ...ll Up 13 A9 L 38 WE1 H 63 P54 Hi Z 88 D7 Pull Up 14 A8 L 39 WE0 H 64 P53 Hi Z 89 D6 Pull Up 15 VDD 40 RE H 65 P52 Hi Z 90 D5 Pull Up 16 A7 L 41 VDD 66 P51 Hi Z 91 D4 Pull Up 17 A6 L 42 EXMOD1 Input 67 P50 Hi Z 92 VDD 18 A5 L 43 EXMOD0 Input 68 P45 Hi Z 93 D3 Pull Up 19 A4 L 44 AVSS 69 VDD 94 D2 Pull Up 20 A3 L 45 AN3 Hi Z 70 P44 Hi Z 95 D1 Pull Up 21 VSS 46 AN2 Hi Z 71 P43 Hi Z 96 D0 Pull Up 22 A2...

Page 455: ...P60 Hi Z 84 P21 Hi Z 10 ADM12 Pull Up 35 VSS 60 VSS 85 VSS 11 ADM11 Pull Up 36 P96 Hi Z 61 NMIRQ Hi Z 86 VDD2 VPP 12 ADM10 Pull Up 37 P95 Hi Z 62 P55 Hi Z 87 P20 Hi Z 13 ADM9 Pull Up 38 WE1 H 63 P54 Hi Z 88 P17 Hi Z 14 ADM8 Pull Up 39 WE0 H 64 P53 Hi Z 89 P16 Hi Z 15 VDD 40 RE H 65 P52 Hi Z 90 P15 Hi Z 16 ADM7 Pull Up 41 VDD 66 P51 Hi Z 91 P14 Hi Z 17 ADM6 Pull Up 42 EXMOD1 Input 67 P50 Hi Z 92 VD...

Page 456: ...endix 14 Appendix E Package Outline The package outline and dimensions of this microcontroller are shown below Package code LQFP100 P 1414 Unit mm Fig E 1 Package Outline 16 00 0 20 16 00 0 20 14 00 0 10 14 00 0 10 ...

Page 457: ... Note Interrupts are prohibited and the bus is locked occupied by the CPU when executing BSET or BCLR however if a BSET or BCLR instruction is executed during program execution in external memory a bus authority release due to an external bus request may be interposed between the data read and data write by the BSET or BCLR instruction If the atomic bus cycles i e bus lock of the BSET or BCLR inst...

Page 458: ... is added to Programming Cautions of MCST The operations of udf02 imm16 Dn and udf02 imm32 Dn are not assured In addition a system error interrupt does not occur in these cases Instruction Format Macro Name MCST9 Dn Following sentences are added to Programming Cautions of MCST9 When udf03 Dm Dn is operated Dm is ignored The operations of udf03 imm8 Dn udf03 imm16 Dn and udf03 imm32 Dn are not assu...

Page 459: ...cessing the unmounted space the operation is not assured Note that it is prohibited to access unmounted space of the internal data space and the internal I O space When accessing the unmounted space the operation is not assured The 2nd line of Operation of various peripheral functions in the low power consumption modes In SLEEP mode all peripheral functions operate except for the bus controller an...

Page 460: ...13 5 and 8 13 6 the DK signal asserted by the read access was changed so as to be negated before the write access ____ ____ Moreover the signal name CSn was changed to CS2 Following sentence is added to 20th line _____ The DK signal connected to the microcontroller should be input so as to be asserted from point EA DW onward and is negated before the next access When the reset state is released SY...

Page 461: ...so as to be asserted from point EA DW onward and is negated before the next access ____ In figure 8 13 27 a and b the DK signal asserted by the low order side access was changed so as to be negated before the high order side access Moreover the figure was changed to one in the case that parameter values were EA 1 and DW 1 ____ In figure 8 13 28 a and b the DK signal was changed so as to be asserte...

Page 462: ...le interrupt is accepted these flags can be cleared by writing to the non maskable interrupt control register NMICR When a flag is set to 1 write a 1 to the flag to clear it Note A non maskable interrupt cannot be generated through software Following sentence is added to under the table shown the change of flag 2 System error interrupt request flag SYSEF This flag cannot be cleared by writing to t...

Page 463: ... 4 13 14 13 15 13 24 13 36 13 45 13 46 13 47 transfer speed transfer rate baud rate Following unit in page1 3 13 3 13 4 13 14 13 15 13 24 13 36 13 46 13 47 bps Conversion accuracy 10 bits 4 LSB Linearity error Note 2 When pin Nos 48 to 45 respectively are In the table 16 6 1 Flash on board write control register Name of FAREG in the table 16 6 1 Flash address register Name of FAREGEX in the table ...

Page 464: ...ial Co Ltd The MN1030F01K is manufactured and marketed under a licensing agreement with Bull CP8 Corporation Note that the MN1030F01K cannot be used on IC cards If you have any inquiries or questions about this book or our semiconductors please contact one of our sales offices listed at the back of this book or Matsushita Electronics Corporation s Sales Department Issued by Matsushita Electric Ind...

Page 465: ...MN103001G F01K LSI User s Manual February 2002 5th Edition Issued by Matsushita Electric Industrial Co Ltd Matsushita Electric Industrial Co Ltd ...

Page 466: ...ALAYSIA Tel 60 3 7951 6601 Fax 60 3 7954 5968 Penang Office Suite 20 07 20th Floor MWE Plaza No 8 Lebuh Farquhar 10200 Penang MALAYSIA Tel 60 4 201 5113 Fax 60 4 261 9989 Johore Sales Office Menara Pelangi Suite8 3A Level8 No 2 Jalan Kuning Taman Pelangi 80400 Johor Bahru Johor MALAYSIA Tel 60 7 331 3822 Fax 60 7 355 3996 Thailand Sales Office Panasonic Industrial THAILAND Ltd PICT 252 133 Muang T...

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