EVBUM2277/D
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15
Line Table 2 (Integration)
Line Table 2 is the Integration timing sequence, during
which the Vertical clocks are inactive and the Horizontal
clocks are running continuously. This sequence runs until
Integration is complete, signaled by the assertion of the
VD_TG signal from the Altera PLD.
Figure 6. Line Table 2 Default Timing
LT2 Entry
V1_CCD
V2_CCD
0
1
Pix Counts
(not to scale)
HCLK_ENABLE
(Vclks not active)
VLOW
VMID
H1A_CCD
H2A_CCD
Line Table 3 (Binning Mode Line Transfer)
Line Table 3 is the Binning Mode Line Transfer sequence,
during which the Vertical clocks are asserted twice per line.
This effectively sums two pixels’ worth of charge into each
Horizontal CCD pixel. After the binning line transfer,
the Horizontal clocks are run in Binning Mode.
Figure 7. Line Table 3 Default Timing
LT3 Entry
V1_CCD
V2_CCD
0
1
2
3
8
1
1
30
1
30
30
Pix Counts
HCLK_ENABLE
VLOW
VMID
VLOW
VMID
H1A_CCD
H2A_CCD
6
T
H
T
VCCD
T
HD
Symbol
4
5
30
1
T
VCCD
7
1
T
VCCD
(not to scale)
Line Table 4 (Trigger Hold)
Line Table 4 is a sequence one pixel time in length, used
when the KSC−1000 is waiting to be triggered by the Altera
PLD. Neither the Vertical clocks nor the Horizontal Clocks
are active during this sequence.
Figure 8. Line Table 4 Default Timing
LT4 Entry
V1_CCD
V2_CCD
0
1
Pix Counts
HCLK_ENABLE
(Vclks not active)
VLOW
VMID
H1A_CCD
H2A_CCD
(Hclks not active)
HLOW
HMID
(LOW)
(not to scale)
