EVBUM2277/D
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12
Table 19. FRAME TABLE 1 DEFAULT SETTING
(continued)
Bit Location
FT1 Entry
Frame Table Data
Bit Location
3
2
1
0
Frame Table Data
13
CLPOB1 Enable
1
0
0
0
14
PBLK Enable
1
0
0
0
15
Pblk_Idle_Val
1
1
1
1
16
Flag
0
1
0
0
17:29
Count
552
0
1
0
30:32
Address 2:0
3
2
1
1
33
Address 3
0
0
0
0
−
Mnemonic
ELT0
ExLTNVD 5
ELT 1
JMPFT 1
Register 9: Line Tables
There are five Line Tables written by default to the
KSC−1000 Line Table registers. Line Table 0 is the normal
Line Transfer sequence. See Figure 4.
Table 20. LINE TABLE 0 DEFAULT SETTING
CCD Signal
Line Table Data Name
LT0 Entry
0
1
2
3
4
5
6
Count[0..12]
1
3
30
2
30
1
0
HCLK_H Enable
0
0
0
0
0
1
0
FDG
V6
0
0
0
0
0
0
0
V5
0
0
0
0
0
0
0
V1
V4
0
0
1
0
0
0
0
V2
V3
0
1
1
1
0
0
0
V2
0
0
0
0
0
0
0
V3RD
V1
0
0
0
0
0
0
0
Line Table 1 is the normal Photodiode Transfer sequence
that transfers charge from all the photodiodes to the vertical
registers. See Figure 5.
Table 21. LINE TABLE 1 DEFAULT SETTING
CCD Signal
Line Table Data Name
LT1 Entry
0
1
2
3
4
5
6
7
Count[0..12]
1
500
6
240
1
400
1310
0
HCLK_H Enable
0
0
0
0
0
0
0
0
FDG
V6
0
0
0
0
0
0
0
0
V5
0
0
0
0
0
0
0
0
V1
V4
0
0
0
1
0
0
0
0
V2
V3
0
1
1
1
1
1
0
0
V2
0
0
0
0
0
0
0
0
V3RD
V1
0
0
1
1
1
0
0
0