EVBUM2277/D
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24
VIDEO SIGNAL PATH
The entire video signal path through the Imager Board and
Timing Board is represented in Figure 19. The individual
blocks are discussed in the Imager Board User Manual and
the Timing Board User Manual.
The hardware gain for the entire pre-AFE signal path can
be calculated by multiplying the gains of the individual
stages:
0.96
1.25
0.5
1.25
+
0.75
(eq. 1)
The gain of the hardware signal path is designed so that the
saturation output voltage of the KAI−2093 CCD will not
overload the AFE input. The AFE default PXGA gain is set
at 1.0 (0.0 dB), and the default VGA gain is set to maximize
the dynamic range of the AFE (See Table 9 and
References
).
Figure 19. Video Signal Path Block Diagram
ÌÌÌÌÌ
VOUT_CCD
+15V
+
−
Emitter−Follower
Av = ~0.96
Op−Amp Buffer
Av = 1.25
Coax Cable
(75ohm, terminated)
Av = 0.5
Digital
Out
Analog
Front End
Op−Amp Buffer
Av = 1.25
+5V
−5V
+
−
+5V
−5V
CCD
AFE (2-stage
prog. gain)
Timing Board
Imager Board
WARNINGS AND ADVISORIES
When programming the Timing Board, the Imager Board
must be disconnected from the Timing Board before power
is applied. If the imager Board is connected to the Timing
Board during the reprogramming of the Altera PLD, damage
to the Imager Board will occur.
Purchasers of a ON Semiconductor Evaluation Board Kit
may, at their discretion, make changes to the Timing
Generator Board firmware. ON Semiconductor can only
support firmware developed by, and supplied by, Truesense
Imaging. Changes to the firmware are at the risk of the
customer.
ORDERING INFORMATION
Please address all inquiries and purchase orders to:
Truesense Imaging, Inc.
1964 Lake Avenue
Rochester, New York 14615
Phone: (585) 784−5500
E-mail: [email protected]
ON Semiconductor reserves the right to change any
information contained herein without notice. All
information furnished by ON Semiconductor is believed to
be accurate.
