ON Semiconductor KAI-2093, User Manual

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EVBUM2277/D
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13
Line Table 2 is the Integration sequence. The vertical
clocks are not active, and the Horizontal register is
continually flushed of charge. See Figure 6.
Table 22. LINE TABLE 2 DEFAULT SETTING
CCD Signal Line Table Data Name
LT2 Entry
0 1
Count[0..12] 1 0
HCLK_H Enable 1 0
FDG V6 0 0
V5 0 0
V1 V4 0 0
V2 V3 0 0
V2 0 0
V3RD V1 0 0
Line Table 3 is the Binning Mode Line Transfer sequence.
Two V1 and V2 pulses occur during each Vertical clocking
interval, followed by Horizontal Register readout. See
Figure 7.
Table 23. LINE TABLE 3 DEFAULT SETTING
CCD Signal Line Table Data Name
LT3 Entry
0 1 2 3 4 5 6 7 8 9
Count[0..12] 1 1 30 1 30 1 30 1 30 0
HCLK_H Enable 0 0 0 0 0 0 0 0 1 0
FDG V6 0 0 0 0 0 0 0 0 0 0
V5 0 0 0 0 0 0 0 0 0 0
V1 V4 0 0 1 0 0 0 1 0 0 0
V2 V3 0 1 1 1 0 1 1 1 0 0
V2 0 0 0 0 0 0 0 0 0 0
V3RD V1 0 0 0 0 0 0 0 0 0 0
Line Table 4 is an Integration sequence. Neither the
Vertical clocks nor the Horizontal clocks are active. See
Figure 8.
Table 24. LINE TABLE 4 DEFAULT SETTING
CCD Signal Line Table Data Name
LT4 Entry
0 1
Count[0..12] 1 0
HCLK_H Enable 0 0
FDG V6 0 0
V5 0 0
V1 V4 0 0
V2 V3 0 0
V2 0 0
V3RD V1 0 0